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參數(shù)資料
| 型號： | ASM5I961CG-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Low Voltage Zero Delay Buffer |
| 中文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 685K |
| 代理商： | ASM5I961CG-32-ET |
July 2005
rev 0.2
ASM5I961C
Low Voltage Zero Delay Buffer
8 of
15
Notice: The information in this document is subject to change without notice.
Table 8: Confidence Factor C
F
CF
Probability of clock edge within the
distribution
0.68268948
± 1
σ
± 2
σ
± 3
σ
± 4
σ
± 5
σ
± 6
σ
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (± 3
σ
) is assumed,
resulting in a worst case timing uncertainty from input to
any output of -275 pS to 315 pS relative to CCLK:
t
SK(PP)
= [–80pS...120pS] + [–150pS...150pS] +
[(15pS _ –3)...(15pS _ 3)] + t
PD
,
LINE(FB)
t
SK(PP)
= [–275pS...315pS] + t
PD
,
LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure
8. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
Figure 8. Max. I/O Jitter versus frequency
Power Consumption of the ASM5I961C and Thermal
Management
The ASM5I961C AC specification is guaranteed for the
entire operating frequency range up to 200MHz. The
ASM5I961C power consumption and the associated long-
term reliability may decrease the maximum frequency
limit, depending on operating conditions such as clock
frequency, supply voltage, output loading, ambient
temperature, vertical convection and thermal conductivity
of package and board. This section describes the impact
of these parameters on the junction temperature and
gives a guideline to estimate the ASM5I961C die junction
temperature and the associated device reliability.
Table 9: Die junction temperature and MTBF
Junction temperature (
°
C)
100
110
120
130
MTBF (Years)
20.4
9.1
4.2
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM5I961C
needs to be controlled and the thermal impedance of the
board/package
should
be
dissipated in the ASM5I961C is represented in equation
1. Where I
CCQ
is the static current consumption of the
ASM5I961C, CPD is the power dissipation capacitance
per output, (M)
Σ
C
L
represents the external capacitive
output load, N is the number of active outputs (N is
always 27 in case of the ASM5I961C). The ASM5I961C
supports driving transmission lines to maintain high signal
integrity and tight timing parameters. Any transmission
line will hide the lumped capacitive load at the end of the
board trace, therefore,
Σ
C
L
is zero for controlled
transmission line systems and can be eliminated from
equation 1. Using parallel termination output termination
results in equation 2 for power dissipation. In equation 2,
P stands for the number of outputs with a parallel or
thevenin termination, V
OL
, I
OL
, V
OH
and I
OH
are a function
of the output termination technique and DC
Q
is the clock
signal duty cycle. If transmission lines are used
Σ
C
L
is
zero in equation 2 and can be eliminated. In general, the
use of controlled transmission line techniques eliminates
the impact of the lumped capacitive loads at the end lines
and greatly reduces the power dissipation of the device.
Equation 3 describes the die junction temperature T
J
as a
function of the power consumption.
optimized.
The
power
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PDF描述 |
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| ASM5I961CG-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961C | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | Low Voltage Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I961CG-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I9653A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
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