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參數(shù)資料
| 型號： | ASM5I961CG-32-ET |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Zero Delay Buffer |
| 中文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | GREEN, TQFP-32 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 685K |
| 代理商： | ASM5I961CG-32-ET |
July 2005
rev 0.2
ASM5I961C
Low Voltage Zero Delay Buffer
6 of
15
Notice: The information in this document is subject to change without notice.
APPLICATIONS INFORMATION
Power Supply Filtering
The ASM5I961C is a mixed analog/digital product and as
such it exhibits some sensitivity that would not
necessarily be seen on a fully digital product. Analog
circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
The ASM5I961C provides separate power supplies for
the output buffers (V
CC
) and the phase–locked loop
(V
CCA
) of the device. The purpose of this design
technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as
an evaluation board this level of isolation is sufficient.
However, in a digital system environment where it is more
difficult to minimize noise on the power supplies a second
level of isolation may be required. The simplest form of
isolation is a power supply filter on the V
CCA
pin for the
ASM5I961C.
Figure 3. illustrates a typical power supply filter scheme.
The ASM5I961C is most susceptible to noise with
spectral content in the 10KHz to 10MHz range. Therefore
the filter should be designed to target this range. The key
parameter that needs to be met in the final filter design is
the DC voltage drop that will be seen between the V
CC
supply and the V
CCA
pin of the ASM5I961C. From the
data sheet the I
CCA
current (the current sourced through
the V
CCA
pin) is typically 2mA (5mA maximum), assuming
that a minimum of 2.375V (V
CC
= 3.3V or V
CC
= 2.5V)
must be maintained on the V
CCA
pin. The resistor RF
shown in Figure 3. must have a resistance of 270
(V
CC
= 3.3V) or 5 to 15
(V
CC
= 2.5V) to meet the voltage
drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the
noise frequency crosses the series resonant point of an
individual capacitor it’s overall impedance begins to look
inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a
low impedance path to ground exists for frequencies well
above the bandwidth of the PLL.
Figure 3. Power Supply Filter
Although the ASM5I961C has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related
problems in most designs.
Driving Transmission Lines
The ASM5I961C clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 15
the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point–to–point distribution of
signals is the method of choice. In a point–to–point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50
resistance to V
CC
/2. This technique draws a fairly high
level of DC current and thus only a single terminated line
can be driven by each output of the ASM5I961C clock
driver. For the series terminated case however there is no
DC current draw, thus the outputs can drive multiple
series terminated lines. Figure 4. illustrates an output
driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the
fanout of the ASM5I961C clock driver is effectively
doubled due to its capability to drive multiple lines.
ASM5I961C
OUTPUT BUFFER
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5. show the simulation
results of an output driving a single line vs two lines. In
both cases the drive capability of the ASM5I961C output
buffer is more than sufficient to drive 50
transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output–to–output skew of
the ASM5I961C. The output waveform in Figure 5. shows
14
IN
OUTA
Z
0
=50
R
S
=36
ASM5I961C
OUTPUT BUFFER
14
IN
OUTB1
Z
0
=50
R
S
=36
OUTB0
Z
0
=50
R
S
=36
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASM5I961CG-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961C | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-ET | Low Voltage Zero Delay Buffer |
| ASM5I961C-32-LT | Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | Low Voltage Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ASM5I961CG-32-LT | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961P-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I961PG-32LR | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:Low Voltage Zero Delay Buffer |
| ASM5I9653A | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:3.3V 1:8 LVCMOS PLL Clock Generator |
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