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參數(shù)資料
| 型號： | AS82527 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL |
| 中文描述： | 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 239K |
| 代理商： | AS82527 |
82527
A.C. Characteristics for 8/16-Bit Multiplexed Intel Modes (Modes 0, 1)
Conditions: V
CC
e
5V
g
10%, V
SS
e
0V, T
A
e b
40
§
C to
a
125
§
C, C
L
e
100 pF
Symbol
Parameter
Min
Max
Conditions
1/t
XTAL
Oscillator Frequency
8 MHz
16 MHz
1/t
SCLK
System Clock Frequency
4 MHz
10 MHz
1/t
MCLK
Memory Clock Frequency
2 MHz
8 MHz
t
AVLL
Address Valid to ALE Low
7.5 ns
t
LLAX
Address Hold after ALE Low
10 ns
t
LHLL
ALE High Time
30 ns
t
LLRL
ALE Low to RD
Y
Low
20 ns
t
CLLL
CS
Y
Low to ALE Low
10 ns
t
QVWH
Data Setup to WR
Y
High
27 ns
t
WHQX
Input Data Hold after WR
Y
High
10 ns
t
WLWH
WR
Y
Pulse Width
30 ns
t
WHLH
WR
Y
High to Next ALE High
8 ns
t
WHCH
WR
Y
High to CS
Y
High
0 ns
t
RLRH
RD
Y
Pulse Width
This time is long enough to initiate a double
read cycle by loading the High Speed
Registers (04H, 05H), but is too short to
READ from 04H and 05H (See t
RLDV
)
RD
Y
Low to Data Valid
(Only for Registers 02H, 04H, 05H)
40 ns
t
RLDV
0 ns
55 ns
t
RLDV1
RD
Y
Low Data to Data Valid (for Registers
except 02H, 04H, 05H)
for Read Cycle without a Previous Write
(1)
for Read Cycle with a Previous Write
(1)
1.5 t
MCLK
a
100 ns
3.5 t
MCLK
a
100 ns
t
RHDZ
Data Float after RD
Y
High
0 ns
45 ns
t
CLYV
CS
Y
Low to READY Setup
Condition: Load Capacitance on the READY
Output: 50 pF
32 ns
40 ns
V
OL
e
1.0V
V
OL
e
0.45V
t
WLYZ
WR
Y
Low to READY Float for a Write Cycle
if No Previous Write is Pending
(2)
145 ns
t
WHYZ
End of Last Write to READY Float for a Write
Cycle if a Previous Write Cycle is Active
(2)
2 t
MCLK
a
100 ns
t
RLYZ
RD
Y
Low to READY Float
(for registers except 02H, 04H, 05H)
for Read Cycle without a Previous Write
(1)
for Read Cycle with a Previous Write
(1)
2 t
MCLK
a
100 ns
4 t
MCLK
a
100 ns
8
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