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參數(shù)資料
| 型號： | AS82527 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL |
| 中文描述： | 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 239K |
| 代理商： | AS82527 |
82527
A.C. Characteristics for 8-Bit Non-Multiplexed Synchronous Mode (Mode 3)
Conditions: V
CC
e
5V
g
10%, V
SS
e
0V, T
A
e b
40
§
C to
a
125
§
C, C
L
e
100 pF
Symbol
Parameter
Min
Max
1/t
XTAL
Oscillator Frequency
8 MHz
16 MHz
1/t
SCLK
System Clock Frequency
4 MHz
10 MHz
1/t
MCLK
Memory Clock Frequency
2 MHz
8 MHz
t
EHDV
E High to Data Valid out of High Speed
Register (02H, 04H, 05H)
55 ns
Read Cycle without Previous Write for
Low Speed Registers
(1)
1.5 t
MCLK
a
100 ns
Read Cycle with Previous Write for
Low Speed Registers
(1)
3.5 t
MCLK
a
100 ns
t
ELDH
Data Hold after E Low for a Read
Cycle
5 ns
t
ELDZ
Data Float after E Low
35 ns
t
ELDV
Data Hold after E Low for a Write Cycle
15 ns
t
AVEH
Address and R/W
Y
to E Setup
25 ns
t
ELAV
Address and R/W
Y
Valid after E Falls
15 ns
t
CVEH
CS
Y
Valid to E High
0 ns
t
ELCV
CS
Y
Valid after E Low
0 ns
t
DVEL
Data Setup to E Low
55 ns
t
EHEL
E Active Width
100 ns
t
AVAV
Start of a Write Cycle after a Previous
Write Access
2 t
MCLK
t
AVCL
Address or R/W
Y
to CS
Y
Low Setup
3 ns
t
CHAI
CS
Y
High to Address Invalid
7 ns
t
COPD
CLKOUT Period
(CD
V
a
1)
*
t
OSC(2)
t
CHCL
CLKOUT High Period
(CD
V
a
1)
*
(/2
t
OSC
b
10
(CD
V
a
1)
*
(/2
t
OSC
a
15
NOTES:
1. Definition of ‘‘Read Cycle without a Previous Write’’: The time between the falling edge of E (for the previous write cycle)
and the rising edge of E (for the current read cycle) is greater than 2 t
MCLK
.
2. Definition of CD
V
is the value loaded in the CLKOUT register representing the CLKOUT divisor.
15
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