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參數(shù)資料
| 型號(hào)： | AS82527 |
| 廠(chǎng)商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL |
| 中文描述： | 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 19/22頁(yè) |
| 文件大小： | 239K |
| 代理商： | AS82527 |
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82527
3. Removed XTAL1 and XTAL2 from the excep-
tions for V
IL
spec. XTAL1 V
IL
is now specified at
min
e b
0.5V, max
e
0.8V. XTAL2 is an output.
4. Removed XTAL1 and XTAL2 from the excep-
tions for V
IH
spec. XTAL1 V
IH
is now specified at
min
e
3.0V, max
e
V
CC
a
0.5V. XTAL2 is an
output.
5. Source and Sink current for TX0 and TX1 were
corrected from minimum values to maximum val-
ues.
6. Mode 2; The t
AVSL
specification was decreased
to 7.5 ns from 33 ns.
7. Mode 2; The t
SLAX
specification was decreased
to 10 ns from 20 ns.
8. Mode 3, Asynchronous; The t
DVCH
specification
was decreased to 20 ns from 32 ns.
9. All modes; Two specifications were added for
CLKOUT.
These
specifications
(CLKOUT Period)
e
(CD
V
a
1)
*
t
OSC
, and t
CHCL
(CLKOUT High Period)
e
min (CD
v
a
1)
(/2
t
OSC
b
10 ns and max (CD
V
a
1)
*
(/2
t
OSC
a
15 ns.
NOTE:
CD
V
represented the value loaded
in the lower nibble of the CLKOUT Register
(1FH).
are
t
COPD
10. Serial Interface Mode; The maximum SCLK (SPI
Clock) rate was increased to 8 MHz from 4.2
MHz. The minimum t
CYC
(1/SCLK) was set at
125 ns from 238 ns to reflect the increased max-
imum SPI clock rate.
11. MODE0/1, the t
WHQX
Specifications was de-
creased to 10 ns from 12.5 ns.
This is the -004 revision of the 82527 data sheet.
The following differences exist between the -003
version and the -004 revision.
1. Remove notice on page 1 concerning Advance
Information Data Sheet.
2. Page 4, AS pin description, add ‘‘pin tied high in
Asycnhronous mode 3’’.
3. Page 4, E pin description, add ‘‘pin tied high in
mode 3’’.
4. Page 5, add V
IH
e
0.7 V
CC
and V
IL
e
0.3 V
CC
for LSIO port pins (pins not used to interface to
host-CPU).
5. Page 6, change Differential Input Threshold
from MAX spec to MIN spec.
6. Page 6, add Input Hysteresis spec for RX0/RX1
e
0V maximum.
7. Page 7, t
LLAX
decreased from 20 ns to 10 ns (to
interface to 20 MHz C196).
8. Page 7, t
QVWH
decreased from 30 ns to 27 ns
(to interface to 20 MHz C196).
9. Page 7, t
WLWH
decreased from 40 ns to 30 ns
(to interface to 20 MHz C196).
10. Page 7, t
RLDV
increased from 45 ns to 55 ns.
11. Page 12, t
CHKH
specification added for V
IH
e
2.8V
e
150 ns.
12. Page 12, t
CHAI
decreased from 10 ns to 7 ns.
13. Page 13, timing diagram for t
AVCL
revised to
show common CL low level.
14. Page 14, t
CHAI
decreased from 10 ns to 7 ns.
19
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