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參數(shù)資料
| 型號： | AS82527 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL |
| 中文描述： | 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大小： | 239K |
| 代理商： | AS82527 |
82527
PIN DESCRIPTION
The 82527 pins are described in this section. Table 1 presents the legend for interpreting the pin types.
Table 1. Pin Type Legend
Symbol
Description
I
Input only pin
O
Output only pin
I/O
Pin can be either input or output
PIN DESCRIPTIONS
Pin Name
Pin Type
Pin Description
V
SS1
Ground
GROUND connection must be connected externally to a V
SS
board plane.
Provides digital ground.
V
SS2
Ground
GROUND connection must be connected externally to a V
SS
board plane.
Provides ground for analog comparator.
V
CC
Power
POWER connection must be connected externally to
a
5V DC. Provides power
for entire device.
XTAL1
I
Input for an external clock. XTAL1 (along with XTAL2) are the crystal
connections to an internal oscillator.
XTAL2
O
Push-pull output from the internal oscillator. XTAL2 (along with XTAL1) are the
crystal connections to an internal oscillator. If an external oscillator is used
XTAL2 must be floated, or not be connected. XTAL2 must not be used as a
clock output to drive other CPUs.
CLKOUT
O
Programmable clock output. This output may be used to drive the oscillator of
the host microcontroller.
RESET
Y
I
Warm Reset: (V
CC
remains valid while RESET
Y
is asserted), RESET
Y
must be
driven to a valid low level for 1 ms minimum.
Cold Reset: (V
CC
is driven to a valid level while RESET
Y
is asserted), RESET
Y
must be driven low for 1 ms minimum measured from a valid V
CC
level. No
falling edge on the reset pin is required during a cold reset event.
CS
Y
I
A low level on this pin enables CPU access to the 82527 device.
INT
Y
(V
CC
/2)
O
O
The interrupt pin is an open-drain output to the host microcontroller. V
CC
/2 is
the power supply for the ISO low speed physical layer. The function of this pin is
determined by the MUX bit in the CPU Interface Register (Address 02H) as
follows:
MUX
e
1: pin 24 (PLCC)
e
V
CC
/2, pin 11
e
INT
Y
MUX
e
0: pin 24 (PLCC)
e
INT
Y
RX0
RX1
I
I
Inputs from the CAN bus line(s) to the input comparator. A recessive level is
read when RX0
l
RX1. A dominant level is read when RX1
l
RX0. When the
CoBy bit (Bus Configuration register) is programmed as a ‘‘1’’, the input
comparator is bypassed and RX0 is the CAN bus line input.
TX0
TX1
O
O
Serial data push-pull output to the CAN bus line. During a recessive bit TX0 is
high and TX1 is low. During a dominant bit TX0 is low and TX1 is high.
4
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