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參數(shù)資料
| 型號： | AS82527 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL |
| 中文描述： | 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 239K |
| 代理商： | AS82527 |
82527
A.C. Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2)
Conditions: V
CC
e
5V
g
10%, V
SS
e
0V, T
A
e b
40
§
C to
a
125
§
C, C
L
e
100 pF
Symbol
Parameter
Min
Max
1/t
XTAL
Oscillator Frequency
8 MHz
16 MHz
1/t
SCLK
System Clock Frequency
4 MHz
10 MHz
1/t
MCLK
Memory Clock Frequency
2 MHz
8 MHz
t
AVSL
Address Valid to AS Low
7.5 ns
t
SLAX
Address Hold after AS Low
10 ns
t
ELDZ
Data Float after E Low
0 ns
45 ns
t
EHDV
E High to Data Valid for Registers 02H,
04H, 05H
0 ns
45 ns
for Read Cycle without a Previous Write
(1)
for Read Cycle with a Previous Write
(for Registers except for 02H, 04H, 05H)
1.5 t
MCLK
a
100 ns
3.5 t
MCLK
a
100 ns
t
QVEL
Data Setup to E Low
30 ns
t
ELQX
Input Data Hold after E Low
20 ns
t
ELDV
E Low to Output Data Valid on Port 1/2
t
MCLK
2 t
MCLK
a
500 ns
t
EHEL
E High Time
45 ns
t
ELEL
End of Previous Write (Last E Low) to E
Low for a Write Cycle
2 t
MCLK
t
SHSL
AS High Time
30 ns
t
RSEH
Setup Time of R/W
Y
to E High
30 ns
t
SLEH
AS Low to E High
20 ns
t
CLSL
CS
Y
Low to AS Low
20 ns
t
ELCH
E Low to CS
Y
High
0 ns
t
COPD
CLKOUT Period
(CD
V
a
1)
*
t
OSC(3)
t
CHCL
CLKOUT High Period
(CD
V
a
1)
*
(/2
t
OSC
b
10 (CD
V
a
1)
*
(/2
t
OSC
a
15
NOTES:
1. Definition of ‘‘Read Cycle without a Previous Write’’: The time between the falling edge of E (for the previous write cycle)
and the rising edge of E (for the current read cycle) is greater than 2 t
MCLK
.
2. Definition of ‘‘Write Cycle with a Previous Write’’: The time between the falling edge of E (for the previous write cycle) and
the falling edge of E (for the current write cycle) is less than 2 t
MCLK
.
3. Definition of CD
V
is the value loaded in the CLKOUT register representing the CLKOUT divisor.
11
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