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參數(shù)資料
| 型號： | AS4C256K16FO |
| 廠商： | Alliance Semiconductor Corporation |
| 英文描述： | 5V 256K × 16 CMOS DRAM (Fast Page Mode)(5V 256K × 16 CMOS動態(tài)RAM（快速頁面模式）) |
| 中文描述： | 5V的256K × 16的CMOS的DRAM（快速頁面模式）（5V的256K × 16的CMOS動態(tài)隨機存儲器（快速頁面模式）） |
| 文件頁數(shù)： | 2/25頁 |
| 文件大?。?/td> | 521K |
| 代理商： | AS4C256K16FO |
AS4C256K16FO
2/1/01;
V.0.9
Alliance Semiconductor
P. 2 of 25
Functional description
The AS4C256K16FO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) device organized as
262,144 words × 16 bits. The AS4C256K16FO is fabricated with advanced CMOS technology and designed with innovative
design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels.
The AS4C256K16FO features a high-speed page mode operation in which high speed read, write and read-write are performed
on any of the 512
×
16 bits defined by the column address. The asynchronous column address uses an extremely short row
address capture time to ease the system-level timing constraints associated with multiplexed addressing. Output is tri-stated by a
column address strobe (CAS) which acts as an output enable independent of RAS. Very fast CAS to output access time eases
system design.
Refresh on the 512 address combinations of A0–A8 during an 8 ms period is accomplished by performing any of the following:
RAS-only refresh cycles
Hidden refresh cycles
CAS-before-RAS refresh cycles
Normal read or write cycles
Self-refresh cycles.
*
The AS4C256K16FO is available in standard 40-pin plastic SOJ and 44-pin TSOP II packages compatible with widely available
automated testing and insertion equipment. System level features include single power supply of 5V ± 10% tolerance and direct
interface with TTL logic families.
Logic block diagram
Recommended operating conditions
Parameter
* Self-refresh option is available for new generation device only. Contact Alliance for more information.
Symbol
Min
Typ
Max
Unit
Supply voltage
V
CC
GND
4.5
5.0
5.5
V
0.0
0.0
0.0
V
Input voltage
V
IH
V
IL
2.4
–
V
CC
+ 1
0.8
V
–1.0
–
V
512
×
512
×
16
array
(4,194,304)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
GND
A
R
Column decoder
OE
RAS
UCAS
LCAS
WE
I/O0 to I/O15
Substrate
bias generator
Data
I/O
buffer
R
c
RAS clock
generator
CAS clock
generator
WE clock
generator
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| AS4C4M4EOQ | 4M × 4 CMOS QuadCAS DRAM(EDO) Family(4M × 4 CMOS QuadCAS動態(tài)RAM（擴展數(shù)據(jù)總線）) |
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| AS4C4M4F1 | 5V 4M×4 CMOS DRAM （Fast Page Mode)(5V 4M×4 CMOS 動態(tài)RAM（快速頁面模式）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS4C256K16FO50JC | 制造商: 功能描述: 制造商:undefined 功能描述: |
| AS4C256K16FO-50JC | 制造商:Alliance Memory Inc 功能描述: |
| AS4C256K16FO-50JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256K X 16 CMOS DRAM (Fast Page Mode) |
| AS4C256K16FO-50TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256K X 16 CMOS DRAM (Fast Page Mode) |
| AS4C256K16FO-50TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V 256K X 16 CMOS DRAM (Fast Page Mode) |
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