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| 型號： | AND8090D |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | AC Characteristics of ECL Devices |
| 中文描述： | 交流特性的ECL裝置 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 896K |
| 代理商： | AND8090D |
AND8090/D
http://onsemi.com
16
As an example, the NBSG14 data sheet specifies the
typical CycletoCycle Jitter as 0.5 ps RMS which is the one
sigma value.
Total RJ Test Setup
The test setup shown in Figure 38 is used to sample edge
locations over a large number of periods, and then measure
the total RMS random jitter.
Total Jitter (RJ)
[Pattern Generator (RJ)]2
[DUT (RJ)]2
[Oscilloscope (RJ)]2
Figure 38. Total Random Jitter Test
50% Duty
Trigger
Pattern Generator
Oscilloscope
RJ (RMS)
50% Duty
DUT
Cycle Pulse
Cycle Pulse
Test Equipment RJ Test Setup
The test setup shown in Figure 39 is used to measure the test equipment RMS random jitter.
Test Equipment Jitter (RJ)
[Pattern Generator (RJ)]2
[Oscilloscope (RJ)]2
Figure 39. Test Equipment Random Jitter Test
50% Duty Cycle Pulse
Trigger
Pattern Generator
Oscilloscope
RJ (RMS)
DUT RJ Calculation
The DUT RMS random clock jitter determined with the following equation is specified as CycletoCycle Jitter.
DUT (RJ)
[Total Jitter (RJ)]2
[Test Equipment Jitter (RJ)]2
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