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| 型號： | AND8090D |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | AC Characteristics of ECL Devices |
| 中文描述： | 交流特性的ECL裝置 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 896K |
| 代理商： | AND8090D |
AND8090/D
http://onsemi.com
13
Negative Setup and Positive Hold Example
– The
MC100E445 4Bit Serial/Parallel Converter data sheet
specifies the following:
The minimum setup time of negative 200 ps indicates
that the left edge of the timing window is 200 ps after
the active rising clock edge.
The minimum hold time of positive 300 ps specifies
that the right edge of the timing window is 300 ps after
the active rising clock edge.
The setup time requirement and the hold time requirement
were both met in the example shown in Figure 33, therefore
the LOWtoHIGH output transition occurs after the CLK
rising edge propagation delay of 1800 ps. Note that the input
cannot change within the timing window of 100 ps. Only
one of the differential clocks and differential inputs is shown
in Figure 33.
Positive Setup and Negative Hold Example
– The
MC100E136 6Bit Universal Up/Down Counter data sheet
specifies the following:
The minimum setup time of positive 400 ps indicates
that the left edge of the timing window is 400 ps before
the active rising clock edge.
The minimum hold time of negative 250 ps specifies
that the right edge of the timing window is 250 ps
before the active rising clock edge.
The setup time requirement and the hold time requirement
were both met in the example shown in Figure 34, therefore
the LOWtoHIGH output transition occurs after the CLK
rising edge propagation delay of 1150 ps. Note that the input
cannot change within the timing window of 150 ps.
Figure 33. Negative Setup and Positive Hold Example
t
(ps)
CLK
50%
50% 50%
INPUT
OUTPUT
t
PLH
1800 ps
200
t
s(min)
+300
t
h(min)
50%
Figure 34. Positive Setup and Negative Hold Example
t
(ps)
CLK
50%
50%
50%
INPUT
OUTPUT
t
PLH
1150 ps
+400
t
s(min)
250
t
h(min)
50%
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