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參數(shù)資料
| 型號： | AN701 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller |
| 中文描述： | 設計高頻型DC - DC轉(zhuǎn)換器隨著Si9114A開關(guān)模式控制器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 1113K |
| 代理商： | AN701 |
AN701
Vishay Siliconix
Document Number: 70575
16-Jan-01
www.vishay.com
7
Figure 12.
Constant Frequency Current Mode Control
OSC
V
C
1
2
3
R
SENSE
I
D
L
iL
V
OUT
iL
iDC
I
D
V
C
Waveform A has an ideal textbook appearance, but is in fact
rarely encountered. Waveforms B and C are typical yet close
to the threshold limit, and thus could lead to instability. The
addition of a simple RC network on the sensed waveform
suppresses this leading-edge spike. The low pass filter should
be selected so that only the leading-edge spike is suppressed
and the overall waveform is not distorted. The waveform must
contain a clean rising slope for the error amplifier to intersect.
If the RC time constant is too long, then the waveform will be
distorted and lead to falling-edge jitter on the turn-off edge.
Slope compensation can also be used to eliminate noise or
jitter. A sample of the oscillator voltage is superimposed on the
error amplifier to produce a clean crossing of the thresholds
and to avoid any hunting.
The Si9114A has built-in leading-edge blanking/ suppression
to eliminate some of the effects of these spikes. The two
comparators used to operate the circuit have different delay
times as follows:
The current mode comparator needs more noise immunity,
and therefore has a deliberately slower delay time to block
out noise and spikes which are present on the leading
edge. Typical delay times should be around 100 ns.
The peak current limiting comparator has the fastest
response time, since it is used only to protect the circuit in
the event of an overload. The delay times for this
comparator should be around 70 ns.
(%
(
When designing converters for high switching frequency, a
certain discipline is required to determine the right choice of
components. This process should be an iterative choice and
the board layout should be properly planned before CAD
layout is undertaken.
Figure 13
Current Waveforms
A
B
C
Figure 14
Current Sense Filtering Network
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