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參數(shù)資料
| 型號(hào)： | AN701 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller |
| 中文描述： | 設(shè)計(jì)高頻型DC - DC轉(zhuǎn)換器隨著Si9114A開關(guān)模式控制器 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 1113K |
| 代理商： | AN701 |
AN701
Vishay Siliconix
www.vishay.com
4
Document Number: 70575
16-Jan-01
Typical open loop voltage gain is 77 dB, and unity gain
bandwidth is typically 2.7 MHz. The soft-start circuit (see Pin 7
description) forces the output to within 0.7 V above ground,
and additional clamp diodes limit the positive output excursion
to within 2xV
BE
above V
REF .
Operation at high frequency
allows high closed loop bandwidths and permits excellent
transient response to both input and output changes. Under
normal operation, a small 100 pF bypass capacitor is
recommended from N
INV
to Comp to increase high-frequency
noise rejection. This should be calculated, however, in
conjunction with the loop dynamics.
!
The soft-start circuit is designed to help dc-to-dc converters
start in an orderly manner and reduce component stress. The
output of the error amplifier is clamped by a PNP transistor.
The external capacitor C
SS
is supplied by a 20- A current
source and will charge linearly to 4.6 V. In the event of an
under-voltage lockout (or during start-up), this capacitor is held
low.
Figure 5
Soft-Start
Feedback
Comparator
UV-low
V
REF
4.6 V
20 A
C
SS
Error Amp
Soft-start is a very important feature and has many beneficial
effects, especially in applications connecting to telecom lines
where source impedances are high. In such cases, there is an
initial start-up current caused by the input capacitor, followed
by a secondary peak caused by the converter running at
maximum duty cycle while trying to reach regulation. Where
large output capacitances and peak loads are encountered,
oscillations may occur. These can be prevented with the use
of long soft-start times. The soft-start pin can also be used as
a non-latching shutdown pin by connecting it to
–
V
IN
. This
approach allows a shutdown with soft re-start.
"#
The oscillator circuit uses external timing components R
T
and
C
T
. An internal divide-by-two prevents pulses with greater than
50% duty cycle, so that core saturation can be avoided. When
the R
T
terminal is connected to V
CC
, comparator C
2
disconnects the oscillator output from the SYNC terminal using
SW
1
, and allows an external oscillator circuit to take control of
the current mode comparator circuit.
The current programmed by R
T
defines the charging current of
C
T
and the on and off times with the following design
equations:
t
ON
1.025 x R
T
x C
T
8
t
OFF
5 x R
ql
x C
T
f
OSC
1
2x
1
t
ON
t
OFF
(1)
(2)
(3)
where R
ql
= 25
Actual values taken from a prototype board have been
plotted (Figure 6), and are a close match (except for 47 pF,
where stray parasitics have more significant effect).
(
f
R
OSC
(k )
1000
10
100
10
100
1000
Note: These curves were measured in
a board with 3.5 pF of
external parasitic capacitance.
Figure 6
Oscillator Frequency Selection
47 pF
200 pF
100 pF
150 pF
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