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參數(shù)資料
| 型號： | AN701 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller |
| 中文描述： | 設(shè)計高頻型DC - DC轉(zhuǎn)換器隨著Si9114A開關(guān)模式控制器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 1113K |
| 代理商： | AN701 |
AN701
Vishay Siliconix
Document Number: 70575
16-Jan-01
www.vishay.com
5
Figure 7
Oscillator
I
1
C
1
V
REF
C
2
I
2
Q
2
B
1
B
2
B
3
SW
1
Q
1
C
T
R
T
U
1
D
Q
Q
CLK
SYNC
Figure 8
Oscillator Synchronization
+V
IN
SHD
V
REF
NI
FB
COMP
SS
V
Sense
Out
–
V
IN
SYNC
C
OSC
R
OSC
Si9114A
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Si9114A
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Si9114A
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Rt
Ct
IC1
IC2
IC3
+V
IN
SHD
V
REF
NI
FB
COMP
SS
V
Sense
Out
–
V
IN
SYNC
C
OSC
R
OSC
+V
IN
SHD
V
REF
NI
FB
COMP
SS
V
Sense
Out
–
V
IN
SYNC
C
OSC
R
OSC
V
CC
R
120 k
C
1 F
C
T
–
V
IN
R
t
C
t
R
68 k
SW
1
SW
1
Closed = Frequency High
SW
1
Open = Frequency Low
Figure 9
Frequency Shifting Using R
t
Current Change
D
1
In certain circumstances, such as current limiting, it may be
desirable to change the frequency of the converter for a period
of time to overcome current tails (see Figure 16 for further
explanation). With the Si9114A, this is easily done by adding
or subtracting some current into the R
T
terminal:
The charging current in C
T
is set by 8
R
T.
The voltage at the R
T
terminal is 4 V, as supplied by an
internal emitter follower from the reference.
The frequency can be changed easily by supplying some of
the current into R
T
from the V
CC
rail, thus
“
starving
”
the
internal current source, and slowing the frequency down.
The current in R
T
is set by V = IR where V = 4 V and R = R
T
.
Using a diode, and some type of switch, the frequency can be
easily changed: when SW
1
is closed, D
1
is reverse biased, and
has no effect on R
T
. When SW
1
is open, current flows through
R
1
and D
1
into R
T
and removes some of the current supplied
by the internal emitter follower.
$%&
The
SYNC
input allows operation from a master clock as the
connection is made after the divide-by-two. As a result,
synchronization in both frequency and phase is possible. This
unique feature is important to systems designers who use
multiple
converters,
where
unsynchronized
“
beating
”
effect is present and causes difficult
EMI/EMC problems. If an external clock is used, duty cycles of
>50% are possible due to the position of the
SYNC
pin , after
the divide-by-two. Where >50% conduction is used, core reset
must be allowed, in order to prevent core saturation.
Synchronization is in master/slave mode, with one device (the
“
master
”
) setting the switching frequency and others (the
“
slaves
”
) with disabled oscillators locked to it. Alternatively, all
devices can be clocked using a master oscillator.
noise
caused
by
an
During slave mode, the unused C
T
pin should be connected to
ground, and the R
T
to V
CC
.
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