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參數(shù)資料
| 型號： | AN701 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Designing High-Frequency DC-to-DC Converters With the Si9114A Switchmode Controller |
| 中文描述： | 設(shè)計(jì)高頻型DC - DC轉(zhuǎn)換器隨著Si9114A開關(guān)模式控制器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 1113K |
| 代理商： | AN701 |
AN701
Vishay Siliconix
Document Number: 70575
16-Jan-01
www.vishay.com
3
Figure 3
Shutdown
UV-Low
Q
R
S
20 A
V
CC
6
5
4
3
2
1
NC
–
OP
+OP
TL431
Si9114A
V
out
SHUTDOWN
The shutdown pin is configured to allow fast latched
termination of the output pulse. The delay from shutdown to
output is typically 300 ns. This delay is short enough to allow
this pin to be used for over-voltage applications where fast
orderly shutdown is desirable: for example, when control of the
feedback loop is lost.
Using an opto-coupler and a TL431, interface is easy. (See 3)
Once latched, the shutdown can only be reset from the UVLO
circuit by re-cycling the power. In the event of an over-voltage,
the latch can be reset by momentarily pulling the V
CC
to a value
lower than the UVLO threshold.
This approach will generally be acceptable, since the
feedback winding will not be supplying power, and the only
power maintaining the latch will be supplied by the depletion
start transistor. Note, however, that this action will still be
subject to the power dissipation limits of the Si9114A package
and should ideally be applied as a short fast pulse.
An internal 20- A current source pull-up on SHUTDOWN pin
is provided. However, if the Si9114A is used in a potentially
noisy environment, a 10-k pull-up is recommended from
SHUTDOWN to V
CC
to prevent fault triggering, and to prevent
a start-up problem when a fast slew rate power supply (dv/dt
> 100 V/ms) is used for +V
IN
(pin 1).
The reference voltage is a fully buffered band gap type which
can source 5 mA over the specified voltage tolerance range.
The reference should be well de-coupled to prevent instability
and jitter. A ceramic 100 nF or small tantalum is recommended,
depending on the de-coupling present on the supply pins.
Figure 4
Operational Amplifier
+
–
FBK
NINV
Soft
Star
t
1.5 k
Comp
The error amplifier consists of a PMOS input folded cascade
gain stage followed by a class AB unity gain amplifier.
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