
34
SDF00034AEB
AN32502A
Publication data: November 2002
34
36
35
31
30
29
7bit
DAC
OSC
CTL
VB1
33
32
VB1
VB2
335k
640k
VREFH
1.95 V
SSWC
6
R101
R102
R103
R11
R12
R
C
C
L1
Q11
Q12
C
D
HO1
LO1
PGND1
FBR1
SGND
I
F
S
OUTPUT
+
-
4K
Error
amplifier
PWM
comparator
Buffer
Output
stage
Figure 6
1
Ch.1 is a step-down DC-DC converter. Figure 6
1 shows an internal block configuration.
1) Output setting
Built-in a 7-bit DA converter, it allows you to set a reference voltage by the step of about 8.36 mV.
In comparison between this reference voltage and FBR1 pin input voltage, a feedback control functions.
Therefore, output voltage is determined by the following equation:
V
OUT
=
V
REF
is 1.08 V of an initial setting. (DAC data ‘1010100’)
A voltage variable range is 0.38 V to 1.45 V, allowing for setting with 8.36 mV/ step (value in case of design).
Refer to figure 6
3 for linearity of DAC.
When high precision is required for output voltage, use a high precision resistor for R11 and R12, respectively.
R11 and R12 are influenced not by absolute precision, but by relative precision. Therefore, when using a resistor of
±
0.5%
precision resistor, output voltage varies for maximum
±
1%.
2) PWM comparison block
PWM comparator controls the on period of output pulse depending on input voltage.
Set output voltage to “High” and power on N-channel output MOS while triangular wave oscillation voltage is lower than
pin 36 (SS1) and pin 34 (error amplifier output) voltages.
Maximum duty is determined by maximum voltage of triangular oscillation and set voltage of pin 36 (SS1). This IC is set to
about 88%.
Insertion of a capacitor between pin 36 and GND allows for a soft start operation enabling a gradual elongation of on period
of output pulse and making overshoot and undershoot smaller at the time of startup. The constant at the soft start is
determined by internal R101 and an external capacitor of pin 36.
R11
+
R12
R12
×
V
REF
Application Notes (continued)
6
.
Explanation of operation
Ch.1