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| 型號(hào)： | AN3729 |
| 英文描述： | MA31750 - Bus arbiter |
| 中文描述： | MA31750 -總線(xiàn)仲裁器 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大小： | 54K |
| 代理商： | AN3729 |
AN3726: MA31750 - Application Note 3
1/5
The following information applies to the N- iteration of the
MA31750.
Console Mode is an optional feature of MIL-STD-1750
processors in general and is mentioned in MIL-STD-1750.
The mode is provided within the MA31750 to allow the system
designer to control, monitor and modify internal operation of
the processor without having to substantially rewrite system
software. This Applications Note describes this mode in detail,
giving information on the commands available and the external
hardware required to support the Console. This Note updates
and corrects the previous issues for the relevant iterations.
OVERVIEW
The processor can operate in one of a number of different
modes. One of these is Console mode where the normal MIL-
STD-1750 operation is suspended and a special debugging
interface is presented instead.
Console mode may be entered by either hardware or
software means. When in Console mode the processor
receives its instructions from a fixed IO-mapped location.
Operands and results (as appropriate) associated with these
instructions are passed between system and processor via two
other fixed locations in the IO map. Any number of Console
commands may be performed before issuing a special
command which returns control back to the interrupted 1750
program.
Note that the two interval timers, Timer A and Timer B, are
stopped on entry to Console mode, in accordance with MIL-
STD-1750.
ENTERING CONSOLE MODE USING CONREQN
Asserting CONREQN low for 2 machine cycles during
normal operation will cause the processor to enter Console
mode following the completion of the current instruction (but
see note on Console inhibit). Whilst CONREQN is low, the
device will loop round three machine cycles, one of which will
perform a read of the command register (8402
16
). The
command is not executed whilst CONREQN remains low.
CONREQN may stay low for as long as required. The user
should load the system Console Command register with the
desired command before asserting CONREQN high, at which
point the requested command will be executed. The flowchart
shows the remainder of the command operation. See Table 1
for command information.
ENTERING CONSOLE MODE WITH BPT
If the processor encounters a BPT instruction the
processor will enter Console mode (but see note on Console
inhibit) and will immediately process the Console command
contained in the Command register. It is important, therefore,
that the Command register is loaded before any BPT
instructions may be encountered. Operation then continues
as for CONREQN-initiated commands (see flowchart).
CONSOLE INHIBIT
When CONREQN is asserted low, the CPU checks its
internal copy of the configuration register to see if a console is
present. If console is entered via the BPT instruction, the CPU
reads the system configuration word, hence giving dynamic
control over console entry by BPT. If no console is declared in
the configuration, CONREQN is ignored and BPT instructions
are treated as NOPs.
CONTROLLING THE PROCESSOR IN
CONSOLE MODE
When in Console mode the processor communicates with
the system console via a number of locations in IO space, as
listed below:
Address
8402
16
C000
16
4000
16
C001
16
4001
16
The user should provide a method of supplying values
when these addresses are polled by the processor. A typical
approach is to implement three IO-mapped registers which
respond to the above addresses and which may be loaded
from an external controller or banks of switches.
The required action is communicated to the processor by
placing the appropriate command at IO location 8402
16
and
asserting CONREQN high. If the command takes an operand
(such as a value to Write Register) then this should first be
placed at location C000
16
. Following completion of the
command, any results are returned via location 4000
16
. Note
that during XIO and Next XIO operations, external read XIO
commands execute an extra read of the Data input register.
This does not affect the operation in any way. Also note that
the IO addresses C001
16
and 4001
16
are enabled when
Console mode is selected, but is not used as part of the
Console Mode operation.
Following the execution of the first command, the
processor will halt (provided the command is not ‘continue’)
and wait for a further negative edge on CONREQN. The next
command to be executed should be set at address 8402
16
before the rising edge of CONREQN. Any number of
commands may be issued in this way, using CONREQN to
control execution and to signal the presence of a new
command code to the processor.
Function
Console command input
Data input
Data output
Read Console Status (not used in MA31750)
Clear Console (not used in MA31750)
LEAVING CONSOLE MODE
To release the MA31750 from Console mode, a ‘continue’
command should be issued. The instruction pipeline will be
refilled with the 1750 instruction immediately following the
point at which the Console request or BPT was registered;
normal instruction execution then resumes from that point.
AN3726
MA31750 - Use Of Console Mode
Application Note
AN3726-4.1 July 2002
Replaces January 2000 version, AN3726-4.0
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