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參數(shù)資料
| 型號： | AN3729 |
| 英文描述： | MA31750 - Bus arbiter |
| 中文描述： | MA31750 -總線仲裁器 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 54K |
| 代理商： | AN3729 |
AN3726: MA31750 - Application Note 3
2/5
SINGLE STEP
Single step operation is also accomplished using a
‘continue’ command. Once Console mode has been entered,
raising CONREQN will cause the processor to execute the
command and leave Console mode. If the user reasserts
CONREQN low after the 2nd internal cycle after the read and
before the 2nd pipe-line pre-fetch, then exactly one 1750
instruction will be executed before the processor returns to
Console mode. This allows the processor to step through the
1750 code one instruction at a time.
COMMAND SUMMARY
Table 1 shows a summary of all commands available in
Console mode, with a description of their function. Commands
should be constructed according to Figure 1. It should be
noted that although many of the internal registers are made
available in Console mode, attempting to change them may
produce predictable but unexpected results. In particular,
temporary registers T0, T1 and T9-T11 are used by the
Console interface to store operands such as the IC register
prior to Console Mode entry.
Command
Continue
Function
Resumes normal MIL-STD-1750 operation. This command is also
used for single stepping instructions.
Places the contents of a specified internal register into the Console
Output register (IO address 4000). The register to be accessed is
specified as a value placed in the lower 12 bits of the Command
register according to Table 2.
Places the contents of the Console Input register (IO location C000)
into a specified internal register. The register to be accessed is
specified as a value placed in the lower 12 bits of the Command
register according to Table 2.
Places the contents of the 1750 Fault register into the Console
Output register and then clears the Fault Register.
Copies the contents of the Console Input register to the 1750-
defined Status Word register. Note that the A reg is changed to
200E.
The contents of operand memory space at address A (the contents
of the Alternate Address register) are placed in the Console Output
register.
The contents of the Console Input register are placed in operand
memory space at address A.
Read next memory The contents of the A register is incremented. The contents of
operand memory space at address A are then placed in the Console
Output register.
Write next memory
The contents of the A register is incremented. The contents of the
Console Input register are then placed in operand memory space at
address A.
XIO
The XIO command specified by the content of the A register is
performed using data read from the Console Input register. If the XIO
command is illegal the command is ignored. No Status Word
Processor State checking is performed.
Next XIO
As above, but the command in A is incremented before the XIO is
attempted.
Disable
Console operation is suspended pending a new Console request or
an interrupt. If an interrupt occurs then the Instruction Counter will
be restored and normal MIL-STD-1750 operation will be resumed
with the interrupt service routine.
Reserved
Reserved for internal use by GPS - do not use.
Other...
Any other command not described above is ignored and has no
action. User should reload Command register with correct value as
for a new instruction.
Code
0
Read Register
1
Write Register
2
Read and Clear
Fault Register
Write Status Word
3
4
Read memory
5
Write memory
6
7
8
9
A
B
C
X
Table 1: Console Instructions
0
3
4
10
11
15
Command Code
0000000
Register Code
Figure 1: Command Register Format
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