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參數(shù)資料
| 型號： | AN1218 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | HC05 to HC08 Optimization |
| 中文描述： | 以HC08的優(yōu)化HC05 |
| 文件頁數(shù)： | 9/56頁 |
| 文件大?。?/td> | 417K |
| 代理商： | AN1218 |
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Application Note
Description of the Clock
AN1218 Rev. 2
9
Interrupt Mask Bit I
All timer and external interrupts are disabled when this bit is set.
Interrupts are enabled when the bit is cleared. This bit is
automatically set after any CPU reset.
Negative Bit N
This bit is set after any arithmetic, logical, or data manipulation
operation was negative. In other words, bit 7 of the result of the
operation was a logical one.
Zero Bit Z
The zero bit is set after any arithmetic, logical, or data manipulation
operation was zero.
Carry/Borrow Bit C
The carry/borrow bit is set when a carry out of bit 7 of the accumulator
occurred during the last arithmetic, logical, or data manipulation
operation. The bit is also set or cleared during bit test and branch
instructions and shifts and rotates.
Description of the Clock
In the CPU08, the CPU clock rate is twice that of the address/data bus
rates. The internal CPU08 clock rate is 16 MHz for an 8 MHz HC08. To
maintain a 50% duty cycle CPU clock, the oscillator clock, OSC CLK,
must run twice the rate of the CPU clock. Therefore a 32 MHz OSC
clock is needed to drive an 8 MHz HC08.
The flagship member of the CPU08 family has a phase locked loop
(PLL) synthesizer to generate the 32 MHz signal. It is derived from a
suggested crystal frequency of 4.9152 MHz.
Address/Data Rate =
Z
=
8 MHz
CPU Clock Rate
=
2Z
=
16 MHz
OSC Clock Rate
=
4Z
=
32 MHz
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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