參數(shù)資料
型號(hào)： AN1218
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： HC05 to HC08 Optimization
中文描述： 以HC08的優(yōu)化HC05
文件頁數(shù)： 44/56頁
文件大?。?/td> 417K
代理商： AN1218
Application Note
AN1218 Rev. 2
44
Appendix F — CPU05 and CPU08 Data Movement Code
************************************************************
*
* File : MOVEX.ASM
* Description :
* A user wants to start an application one of
* two different ways. The user sets the
* application on the MCU by the logic level
* of Port D, bit 3. Once out of reset, the
* MCU reads Port D and moves data from ROM
* into the RAM configuration registers
* according to the logic level of bit 3.
* Notes: Comments to the right of some instructions
* give numbers.
* CPU05 - 1st # is CPU05 cycle count
* 2nd # is instruction byte count
* CPU08 - 1st # is CPU08 cycle count
* 2nd # is instruction byte count
* Please consult the CPU08 Reference Manual
* for further details on these instructions
* Code is written for educational
* purposes only
*
************************************************************
* For the purpose of this example, we will be using
* random ctrl registers for the code. They are listed
* below in an equate table
TBL EQU $1000 ; start of table
PORTD EQU $03 ; port D data register
PORTADR EQU
$04
PORTBDR EQU
$05
SPICTRL EQU $0A ; SPI control register
SCICTRL EQU $0E ; SCI control register
TIMCTRL EQU $12 ; Timer control register
; port A data direction register
; port B data direction register
ORG $200
***** If bit 3 = 0 when read, then the table
* starts at $1000
* If bit 3 = 1 when read, then the table
* starts at $1008
*********************************
* HC05 code *
START05 LDA PORTD ;3,2 A
←
(PORTD)
AND #$08 ;2,2 clear A except bit 3
; A = 0 or 8
TAX ;2,1 X
←
(A)
; set the offset of X
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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