
xvi
List of Tables
AMD-K6
-2 Processor Data Sheet
21850I/0—December 1999
Preliminary Information
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
EWBEC Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Valid Masks and Range Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 213
SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . .218
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Boundary Scan Bit Definitions for Model 8/[7:0] . . . . . . . . . . 227
Boundary Scan Bit Definitions for Model 8/[F:8] . . . . . . . . . . 229
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . .230
Supported Tap Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . .241
Operating Ranges for OPN Suffixes AHX, 400AFQ,
and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Absolute Ratings for OPN Suffixes AHX, 400AFQ,
and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
DC Characteristics for OPN Suffixes AHX, 400AFQ,
and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Typical and Maximum Power Dissipation for
OPN Suffixes AHX, 400AFQ, and AFR . . . . . . . . . . . . . . . . . . 257
Operating Ranges for OPN Suffixes AFX and 400AFR . . . . . 258
Absolute Ratings for OPN Suffixes AFX and 400AFR. . . . . . 259
DC Characteristics for OPN Suffixes AFX and 400AFR . . . .259
Typical and Maximum Power Dissipation for
OPN Suffixes AFX and 400AFR . . . . . . . . . . . . . . . . . . . . . . . . 261
A[20:3], ADS#, HITM#, and W/R# Strength Selection . . . . . . 263
CLK Switching Characteristics for 100-MHz Bus Operation . 268
CLK Switching Characteristics for 66-MHz Bus Operation . . 268
Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 270
Input Setup and Hold Timings for 100-MHz Bus Operation . 272
Output Delay Timings for 66-MHz Bus Operation . . . . . . . . . 274
Input Setup and Hold Timings for 66-MHz Bus Operation . . 276
RESET and Configuration Signals for 100-MHz
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
RESET and Configuration Signals for 66-MHz
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 280
Test Signal Timing at 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . 280
Package Thermal Specification for OPN Suffixes AHX,
AFQ, and AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Package Thermal Specification for OPN Suffixes AFX
and 400AFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
321-Pin Staggered CPGA Package Specification . . . . . . . . . . 299
Valid Ordering Part Number Combinations . . . . . . . . . . . . . .301
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.