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參數(shù)資料
| 型號(hào)： | AMBA |
| 廠商： | Atmel Corp. |
| 英文描述： | 32-bit Embedded Core Interface(32位嵌入式總線接口) |
| 中文描述： | 32位嵌入式處理器接口（32位嵌入式總線接口） |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | AMBA |
Bus Interface
9
Timing Diagrams
The following diagrams show the timings for the parameters described in this datasheet. For complete timing diagrams,
see the
“
System Architecture
”
datasheet.
Figure 7.
ASB Bus Master Non-sequential Transfer
For the non-sequential transfer shown above, the address and control signals become valid in the system clock
high phase
before the start of the transfer. An important feature of the AMBA protocol is that it allows for poor output valid times on
non-sequential transfers, which is provided through the automatic insertion of a wait state at the start of every non-sequen-
tial transfer by the decoder.
Figure 8.
ASB Bus Master Sequential Transfer
btran1:0]
System Clock
bwait_in
berror_in
blast_in
n_tran
Response
Start of Transfer
End of Transfer
bprot[1:0]
Non-sequential Control
tovctin
tohctl
tihresp
tisresp
btran1:0]
System Clock
bprot1:0]
bwait_in
berror_in
blast_in
Sequential Control
Response
Start of Transfer
End of Transfer
tohctl
tihresp
tisresp
s-tran
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