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參數(shù)資料
| 型號(hào)： | AMBA |
| 廠商： | Atmel Corp. |
| 英文描述： | 32-bit Embedded Core Interface(32位嵌入式總線接口) |
| 中文描述： | 32位嵌入式處理器接口（32位嵌入式總線接口） |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | AMBA |
Bus Interface
8
The following table indicates the actions that must occur in each state.
Name
Description
Actions
IDLE
The master does not require the bus
and it is not granted.
Internal btran is Address-only
Master clock is enabled
Master address bus is tri-stated
BUSIDLE
The master does not require the bus,
but it has been granted anyway.
Internal btran as indicated by master
Master clock is enabled
Master address bus enable is generated from Granted signal
HOLD
The master requires the bus, but it has
not been granted.
Internal btran is Address-only
Master clock is disabled
Master address bus is tri-stated
ACTIVE
Active state when data transfers occur.
Exiting this state is dependent on the
transfer response.
Internal btran as indicated by master
Master clock enable is derived from BWAIT
Master address bus enable is generated from Granted signal
RETRACT
Retract state, where the rest of the
elements in the system see the transfer
finish, but the bus master is not
advanced.
Internal btran is Address-only
Master clock is disabled
Master address bus enable is generated from Granted signal
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