參數(shù)資料
型號: AMBA
廠商: Atmel Corp.
英文描述: 32-bit Embedded Core Interface(32位嵌入式總線接口)
中文描述: 32位嵌入式處理器接口(32位嵌入式總線接口)
文件頁數(shù): 10/12頁
文件大?。?/td> 145K
代理商: AMBA
Bus Interface
10
A sequential transfer has different timing parameters for
the address and control signal valid times. In a typical bus
master, the output valid times for sequential transfers are
far better than for non-sequential transfers. The output hold
times for address, control and data are identical and inde-
pendent of the transfer type.
The other difference between the sequential and non-
sequential transfers is that during a sequential transfer the
data may be driven during the first phase of the transfer
and hence the data valid parameter is specified from the
falling edge of the system clock.
For an Address-only transfer the address and control sig-
nals may be driven in the clock high phase before the start
of the transfer, or in the case of bus master hand-over may
only be driven during the clock low phase of the transfer
itself. The address and control valid timing parameters are
only relevant when the Address-only transfer is followed
immediately by a sequential transfer and in this case the
address and control signals must be driven such that they
are valid during the low phase of the Address-only transfer,
which in turn means they are valid throughout the clock
high phase that precedes the Sequential transfer.
Figure 9.
ASB Master Address-only Transfer
Figure 10.
ASB Bus Master Arbitration and Reset Signals
The
nreset_r
signal may be asserted asynchronously and so there is no setup and hold parameter relating to the assertion
of the signal. The
AGNT
signal, which is returned from the arbiter changes during the low clock phase.
btran[1:0]
System Clock
bprot[1:0]
bwait
berror
blast
a-tran
Control
DONE
Start of Transfer
End of Transfer
tovctla
tihresp
tisresp
tihnres
nreset_r
agntx
System Clock
tisnres
tisagnt
tihagnt
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