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參數(shù)資料
| 型號： | AMBA |
| 廠商： | Atmel Corp. |
| 英文描述： | 32-bit Embedded Core Interface(32位嵌入式總線接口) |
| 中文描述： | 32位嵌入式處理器接口（32位嵌入式總線接口） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AMBA |
Bus Interface
11
Timing Parameters
The timing parameters related to an ASB bus master operating in an AMBA system are also shown in textual form in the
following two tables. The first details the input signals, while the second details output signals.
Table 2.
Bus Master Input Timing Parameters
Parameter
Description
t
isnres
t
ihnres
t
isresp
t
ihresp
t
isagnt
t
ihagnt
nreset de-asserted setup to rising system clock
nreset de-asserted hold after falling system clock
bwait, berror and blast setup to rising system clock
bwait, berror and blast hold after rising system clock
agnt setup to rising system clock
agnt hold after falling system clock
Table 3.
Bus Master Output Timing Parameters
Parameter
Description
t
ovctin
t
ovctla
t
ohctl
For Non-sequential transfers, bprot[1:0] valid after rising system clock
For Address-only transfers, bprot[1:0] valid after falling system clock
bprot[1:0] hold after rising system clock
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