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參數(shù)資料
| 型號(hào)： | AMBA |
| 廠(chǎng)商： | Atmel Corp. |
| 英文描述： | 32-bit Embedded Core Interface(32位嵌入式總線(xiàn)接口) |
| 中文描述： | 32位嵌入式處理器接口（32位嵌入式總線(xiàn)接口） |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | AMBA |
Bus Interface
7
Figure 6.
Bus Master Main State Machine
Note that the state diagram assumes that once the bus
master has made a request for a transfer, as indicated by
Request
, then
Request
remains asserted until the bus
master has performed a transfer.
As the main bus master state machine operates from the
falling edge of the clock, it is necessary to use latched ver-
sions of the transfer response signals
bwait
,
berror
and
blast
to control the exit from the ACTIVE state.
The reset conditions are not shown on the state diagram
and, in a similar manner to the granted state machine, the
main bus master state machine has a complex reset term.
If
agnt
is asserted during reset, when
nreset
is low, the
bus master is the default bus master and enters the IDLE
state. However, if
agnt
is not asserted during reset then the
bus master enters the IDLE state.
IDLE
HOLD
BUSIDLE
ACTIVE
RETRACT
!Granted &
!Request
!Granted & Request
Granted &
Request
Granted &
!Request
!Granted &
!Request
Granted &
Request
!Granted &
Request
Granted & !Request
!Granted & !Request
!Granted & Request
Granted & Request
Granted &
!Request
WAIT
Granted
!Granted
!Granted
DONE+
LAST+
ERROR
Granted
!Granted
No Transfer Request
Granted
Transfer Request
Granted
No Transfer Request
Not Granted
Transfer Request
Not Granted
RETNEXT
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