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參數(shù)資料
| 型號(hào)： | AMBA |
| 廠商： | Atmel Corp. |
| 英文描述： | 32-bit Embedded Core Interface(32位嵌入式總線接口) |
| 中文描述： | 32位嵌入式處理器接口（32位嵌入式總線接口） |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | AMBA |
Bus Interface
6
Bus Master Interface Description
The bus master interface consists of a state machine that is
used to determine if the master is currently granted the
bus, and to control the bus interface of the master.
Granted State Machine
The granted state machine is used to determine whether or
not the bus master has been granted the bus. It runs on the
rising edge of the system clock and has only two states
GRANTED and NOT_GRANTED. The state diagram is
shown below.
Figure 5.
Bus Master Granted State Machine
The output from the state machine is the internal
Granted
signal, which is used in the main bus master state machine.
It is important to note that the
agnt
signal may be asserted
for a number of clock cycles, but it is only when
agnt
is
asserted and
bwait
is low that the bus master actually
becomes GRANTED.
An important design consideration is that the state machine
may be asynchronously reset into either state depending
on the value of the
agnt
signal. During reset one bus mas-
ter in the system is set as the default bus master, as
indicated by
agnt
being asserted during reset, and will be
reset in to the GRANTED state. All other bus masters will
be reset into the NOT_GRANTED state.
Bus Interface State Machine
The main bus interface state machine is falling edge trig-
gered and contains six states. The entire state diagram, as
shown in Figure 6, is quite complex but can be considered
in four quadrants:
The
“
Transfer Request, Granted
”
quadrant contains three
states, which handle bus turn around and the retract
operation.
The two internal bus master signals
Granted
and
Request
control the majority of the transitions around the state dia-
gram.
Granted
is generated from the simpler state
machine described above and
Request
is generated
directly by the bus master.
Request
is asserted high when
the bus master requires a transfer on the bus and is low
when the bus master does not need access to the bus.
The only time when a transition around the state diagram is
not controlled by
Granted
and
Request
is when the bus
master is in the ACTIVE state. In this state the transition to
the next state is determined by the transfer response that is
received. WAIT, DONE, LAST, ERROR and RETNEXT
shown in the diagram correspond to the encoding of the
transfer response signals.
NOT_GRANTED
Granted = 0
GRANTED
Granted = 1
BWAIT + !AGNT
!BWAIT & AGNT
BWAIT + AGNT
!BWAIT & !AGNT
No Transfer Request
Granted
Transfer Request
Granted
No Transfer Request
Not Granted
Transfer Request
Not Granted
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