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參數(shù)資料
| 型號(hào)： | AMBA |
| 廠商： | Atmel Corp. |
| 英文描述： | 32-bit Embedded Core Interface(32位嵌入式總線接口) |
| 中文描述： | 32位嵌入式處理器接口（32位嵌入式總線接口） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 145K |
| 代理商： | AMBA |
Bus Interface
2
Note:
Scan Test Configuration
The coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order to
achieve this, the ATPG vectors must be generated on the entire circuit (top level) which includes the ARM7TDMI Bus Inter-
face or all ARM7TDMI Bus Interface I/Os must have a top level access and ATPG vectors must be applied to these pins.
1. The scan chain uses the clock BCLK.
Table 1.
Bus Interface Pin Description
Name
Direction
Source/Destination
Description
AMBA Bus Inputs
nreset_r
Input
Reset Controller
System reset for flip-flop working on the rising edge of the System
Clock (nreset_r synchronous to nclock). Active low.
System reset for flip-flop working on the rising edge of the inverted
System Clock (nreset_f synchronous to clock). Active low.
System Clock
Inverted System Clock
Multiplexed BWAIT response from all the peripherals. Active high.
Multiplexed BERROR response from all the peripherals. Active
high.
Multiplexed BLAST response from all the peripherals. Active high.
Bus Grant: indicates that the bus master (ARM7TDMI) will be
granted the bus when BWAIT is low.
AMBA Bus Outputs
nreset_f
Input
Reset Controller
clock
nclock
bwait_in
Input
Input
Input
Slaves + decoder
berror_in
Input
Slaves + decoder
blast_in
Input
Slaves + decoder
agnt
Input
Arbiter
btran[1:0]
Output
Current bus
master/decoder, slaves
Transfer type: type of the next transaction (Address-only, Non-
sequential or Sequential). To be connected to the tri-state bus
BTRAN[1:0] of the ASB.
Protection control: indicates if the transfer is an opcode fetch or
data access, as well as if the transfer is a supervisor mode access
or a user mode access. To be connected to the tri-state bus
BPROT[1:0] of the ASB.
Master address bus enable: indicates when BA bus can be taken
into account. Active high.
ARM7TDMI AMBA Related Signals
bprot[1:0]
Output
Current bus master
mabe
Output
nwait
Output
ARM7TDMI
Not wait: used when accessing slow peripherals to make the
processor wait. Active Low.
Memory abort: tells the processor that a requested access is not
allowed. Active High.
Not memory request: memory access requested by the processor.
Active Low.
Sequential address: next address (memory access) will be related
to the last memory access. Active High.
Not op-code fetch: indicates that the processor is fetching an
instruction from the memory. Active Low.
Not memory translate: indicates that the processor is in user mode.
Active Low.
Scan Test
abort
Output
ARM7TDMI
nMREQ
Input
ARM7TDMI
seq
Input
ARM7TDMI
nopc
Input
ARM7TDMI
ntrans
Input
ARM7TDMI
scan_test_mode
Input
Must be tied to 1 during scan test
Must be tied to 0 in functional mode
Test scan shift enabled when tied to 1
Test scan input (input of the scan chain)
Test scan output (output of the scan chain)
test_se
test_si
(1)
test_so
(1)
Input
Input
Output
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