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參數(shù)資料
| 型號(hào)： | AM79C971VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 74/265頁 |
| 文件大?。?/td> | 3190K |
| 代理商： | AM79C971VCW |
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74
Am79C971
with a pulse width of 60 to 200 ns. This negative excur-
sion may be followed by a positive excursion. This def-
inition is consistent with the expected received signal at
a reverse wired receiver, when a link beat pulse, which
fits the template of Figure 14-12 in the 10BASE-T Stan-
dard, is generated at a transmitter and passed through
100 m of twisted pair cable.
The polarity detection/correction algorithm will remain
armed
until two consecutive frames with valid ETD of
identical polarity are detected. When
armed
, the re-
ceiver is capable of changing the initial or previous po-
larity configuration based on the ETD polarity.
On receipt of the first frame with valid ETD following
H_RESET or Link Fail, the T-MAU will utilize the in-
ferred polarity information to configure its RXD
±
input,
regardless of its previous state. On receipt of a second
frame with a valid ETD with correct polarity, the detec-
tion/ correction algorithm will
lock-in
the received po-
larity. If the second (or subsequent) frame is not
detected as confirming the previous polarity decision,
the most recently detected ETD polarity will be used as
the default.
Note that frames with invalid ETD have no
effect on updating the previous polarity decision.
Once
two consecutive frames with valid ETD have been re-
ceived, the T-MAU will disable the detection/correction
algorithm until either a Link Fail condition occurs or
H_RESET is activated.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when en-
abled by the LED control bits in the Bus Configuration
Registers (BCR4 to BCR7).
Twisted Pair Interface Status
When the T-MAU is in Link Pass state, three signals
(XMT, RCV and COL) indicate whether the T-MAU is
transmitting, receiving, or in a collision state with both
functions active simultaneously. These signals are in-
ternal signals that can be programmed to appear on
any of the LED output pins. Programming is done by
writing to BCR4 to BCR7.
In the Link Fail state, XMT, RCV, and COL are inactive.
Collision Detection Function
Activity on both twisted pair signals (RXD
±
and TXD
±
)
at the same time constitutes a collision, thereby, caus-
ing the internal COL signal to be activated. COL will re-
main active until one of the two colliding signals
changes from active to idle. However, transmission at-
tempt in Link Fail state results in LCAR and CERR in-
dication. COL stays active for 2 bit times at the end of
a collision.
Signal Quality Error Test Function
The Signal Quality Error (SQE) test function (also
called Heartbeat) is disabled when the 10BASE-T port
is selected.
Jabber Function
The Jabber function prevents the twisted pair transmit
function of the T-MAU TXD
±
from being active for an ex-
cessive period of time (20 ms to 150 ms). This prevents
any one node from disrupting the network due to a
stuck-on
or faulty transmitter. If this maximum transmit
time is exceeded, the T-MAU transmitter circuitry is dis-
abled, the JAB bit is set (CSR4, bit 1) and the COL sig-
nal is asserted. Once the transmit data stream is
removed, the T-MAU waits an
unjab
time of 250 ms to
750 ms before it deasserts COL and re-enables the
transmit circuitry.
Power Down
The T-MAU circuitry can be made to go into a power
savings mode. The T-MAU will go into the power down
mode when H_RESET is active, when coma mode is
active, or when the T-MAU is not selected. Refer to the
Power Savings Modes
section for descriptions of the
various power down modes.
Any of the three conditions listed above resets the in-
ternal logic of the T-MAU and places the device into
power down mode. In this mode, the Twisted Pair driver
pins (TXD
±
, TXP
±
) are driven LOW, and the internal
T-MAU status signals (LED0, RCVPOL, XMT, RCV and
COL) signals are inactive.
After coming out of the power down mode, the T-MAU
will remain in the reset state for an additional 10
μ
s. Im-
mediately after the reset condition is removed, the T-
MAU will be forced into the Link Fail state. The T-MAU
will move to the Link Pass state only after 5 to 6 link
beat pulses and/or a single received message is de-
tected on the RD
±
pair.
In snooze mode, the T-MAU receive circuitry will remain
enabled even while the SLEEP pin is driven LOW.
10BASE-T Interface Connection
Figure 37 shows the proper 10BASE-T network inter-
face design. Refer to the
PCnet Family Board Design
and Layout Recommendations Application Note (PID
#19595A)
for more design details. Also, refer to
Appen-
dix A, Am79C971 Compatible Media Interface Modules
for a list of compatible 10BASE-T filter/transformer
modules.
Note:
The recommended resistor values and filter and
transformer modules are the same as those used by
the IMR+ (Am79C981).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKD/W | 制造商:Advanced Micro Devices 功能描述: |
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