- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C971VCW (ADVANCED MICRO DEVICES INC) PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus PDF資料下載
參數(shù)資料
| 型號： | AM79C971VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 72/265頁 |
| 文件大?。?/td> | 3190K |
| 代理商： | AM79C971VCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當(dāng)前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁
72
Am79C971
The time delay from the last rising edge of the message
to IRXEN deassert allows the last bit to be strobed by
IRXCLK and transferred to the controller section, but
prevents any extra bit(s) at the end of message.
Data Decoding
The data receiver is a comparator with clocked output
to minimize noise sensitivity to the DI
±
inputs. Input
error is less than
±
35 mV to minimize sensitivity to input
rise and fall time. IRXCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following IRXCLK. The data receiver also gener-
ates the signal used for phase detector comparison to
the internal MENDEC VCO.
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with
the values 1010b. The clock is phase-locked to the neg-
ative transition at the bit cell center of the second zero
in the pattern.
Since data is strobed at 1/4 bit time, Manchester tran-
sitions which shift from their nominal placement
through 1/4 bit time will result in improperly decoded
data. With this as the criterion for an error, a definition
of Jitter Handling is:
The peak deviation approaching or crossing 1/4 bit
cell position from nominal input transition, for which
the MENDEC section will properly decode data.
Attachment Unit Interface
The Attachment Unit Interface (AUI) is the PLS (Physi-
cal Layer Signaling) to PMA (Physical Medium Attach-
ment) interface which effectively connects the DTE to a
MAU. The differential interface provided by the
Am79C971 controller is fully compliant to Section 7 of
ISO 8802-3 (ANSI/IEEE 802.3) standard.
After the Am79C971 controller initiates a transmission
it will expect to see data
“
looped-back
”
on the DI
±
pair
(when the AUI port is selected). This will internally gen-
erate a
“
carrier sense,
”
indicating that the integrity of
the data path to and from the MAU is intact, and that the
MAU is operating correctly. This
“
carrier sense
”
signal
must be asserted before end of transmission. If
“
carrier
sense
”
does not become active in response to the data
transmission, or becomes inactive before the end of
transmission, the loss of carrier (LCAR) error bit will be
set in the transmit descriptor ring (TMD2, bit 27) after
the frame has been transmitted.
Differential Input Termination
The differential input for the Manchester data (DI
±
) is
externally terminated by two 40.2-
resistors and one
optional common-mode bypass capacitor, as shown in
Figure 36. The differential input impedance, Z
IDF
, and
the common-mode input impedance, Z
ICM
, are speci-
fied so that the Ethernet specification for cable termina-
tion impedance is met using standard 1% resistor
terminators. If SIP devices are used, 39 ohms is also a
suitable value. The CI
±
differential inputs are termi-
nated in exactly the same way as the DI
±
pair.
Figure 36.
AUI Differential Input Termination
Collision Detection
A MAU detects the collision condition on the network
and generates a 10-MHz differential signal at the CI
±
inputs. This collision signal passes through an input
stage which detects signal levels and pulse duration.
When the signal is detected by the MENDEC, it sets the
ICLSN line HIGH. The condition continues for approxi-
mately 1.5 bit times after the last LOW-to-HIGH transi-
tion on CI
±
.
Twisted-Pair Transceiver
This section describes operation of the Twisted-Pair
Transceiver (T-MAU) when operating in half-duplex
mode. When in half-duplex mode, the T-MAU imple-
ments the MAU functions for the Twisted Pair Medium
as specified by the supplement to the IEEE 802.3 stan-
dard (Type 10BASE-T). When operating in full-duplex
mode, the MAC engine behavior changes as described
in the section
Full-Duplex Operation
.
The T-MAU provides twisted pair driver and receiver cir-
cuits, including on-board transmit digital predistortion
and receiver squelch, and a number of additional fea-
tures including Link Status indication, Automatic
Twisted Pair Receive Polarity Detection/Correction and
Indication, Receive Carrier Sense, Transmit Active, and
Collision Present indication.
Twisted Pair Transmit Function
The differential driver circuitry in the TXD
±
and TXP
±
pins provides the necessary electrical driving capability
and the pre-distortion control for transmitting signals
over maximum length Twisted Pair cable, as specified
by the 10BASE-T supplement to the ISO 8802-3 (IEEE/
Am79C971
DI+
DI-
40.2
40.2
0.01
μ
F
to
0.1
μ
F
AUI Isolation
Transformer
20550D-39
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C971 | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKD/W | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。