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參數(shù)資料
| 型號： | AM79C971VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| 中文描述： | 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁數(shù)： | 102/265頁 |
| 文件大?。?/td> | 3190K |
| 代理商： | AM79C971VCW |
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102
Am79C971
Reset
There are three different types of RESET operations
that may be performed on the Am79C971 device,
H_RESET, S_RESET, and STOP. The following is a de-
scription of each type of RESET operation.
H_RESET
Hardware Reset (H_RESET) is an Am79C971 reset
operation that has been created by the proper asser-
tion of the RST pin of the Am79C971 device. When the
minimum pulse width timing as specified in the RST pin
description has been satisfied, then an internal reset
operation will be performed.
H_RESET will program most of the CSR and BCR reg-
isters to their default value. Note that there are several
CSR and BCR registers that are undefined after
H_RESET. See the sections on the individual registers
for details.
H_RESET will clear all registers in the PCI configura-
tion space. H_RESET will cause the microcode pro-
gram to jump to its reset state. Following the end of the
H_RESET operation, the Am79C971 controller will at-
tempt to read the EEPROM device through the EE-
PROM interface. H_RESET resets the T-MAU into the
Link Fail state.
H_RESET will clear DWIO (BCR18, bit 7) and the
Am79C971 controller will be in 16-bit I/O mode after
the reset operation. A DWord write operation to the
RDP (I/O offset 10h) must be performed to set the de-
vice into 32-bit I/O mode.
S_RESET
Software Reset (S_RESET) is an Am79C971 reset op-
eration that has been created by a read access to the
Reset register, which is located at offset 14h in Word
I/O mode or offset 18h in DWord I/O mode from the
Am79C971 I/O or memory mapped I/O base address.
S_RESET will reset all of or some portions of CSR0, 3,
4, 15, 80, 100, and 124 to default values. For the iden-
tity of individual CSRs and bit locations that are af-
fected by S_RESET, see the individual CSR register
descriptions. S_RESET will not affect any PCI configu-
ration space location. S_RESET will not affect any of
the BCR register values. S_RESET will cause the mi-
crocode program to jump to its reset state. Following
the end of the S_RESET operation, the Am79C971
controller will not attempt to read the EEPROM device.
S_RESET does not affect the status of the T-MAU.
After S_RESET, the host must perform a full re-initial-
ization of the Am79C971 controller before starting net-
work activity. S_RESET will cause REQ to deassert
immediately. STOP (CSR0, bit 2) or SPND (CSR5, bit
0) can be used to terminate any pending bus master-
ship request in an orderly sequence.
S_RESET terminates all network activity abruptly. The
host can use the suspend mode (SPND, CSR5, bit 0)
to terminate all network activity in an orderly sequence
before issuing an S_RESET.
STOP
A STOP reset is generated by the assertion of the STOP
bit in CSR0. Writing a 1 to the STOP bit of CSR0, when
the stop bit currently has a value of 0, will initiate a STOP
reset. If the STOP bit is already a 1, then writing a 1 to
the STOP bit will not generate a STOP reset.
STOP will reset all or some portions of CSR0, 3, and 4
to default values. For the identity of individual CSRs and
bit locations that are affected by STOP, see the individ-
ual CSR register descriptions. STOP will not affect any
of the BCR and PCI configuration space locations.
STOP will cause the microcode program to jump to its
reset state. Following the end of the STOP operation,
the Am79C971 controller will not attempt to read the
EEPROM device. Setting the STOP bit does not affect
the T-MAU.
Note:
STOP will not cause a deassertion of the REQ
signal, if it happens to be active at the time of the write
to CSR0. The Am79C971 controller will wait until it
gains bus ownership and it will first finish all scheduled
bus master accesses before the STOP reset is exe-
cuted.
STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to ter-
minate all network activity in an orderly sequence before
setting the STOP bit.
Software Access
PCI Configuration Registers
The Am79C971 controller implements a 256-byte con-
figuration space as defined by the PCI specification
revision 2.1. The 64-byte header includes all registers
required to identify the Am79C971 controller and its
function. Additional registers are used to setup the con-
figuration of the Am79C971 controller in a system.
None of the device specific registers located at offsets
40h through FCh are implemented. The layout of the
Am79C971 PCI configuration space is shown in Table
19.
The PCI configuration registers are accessible only by
configuration cycles. All multi-byte numeric fields follow
little endian byte ordering. All write accesses to Re-
served locations have no effect; reads from these loca-
tions will return a data value of 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKD/W | 制造商:Advanced Micro Devices 功能描述: |
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