178
Am79C971
P R E L I M I N A R Y
Read/Write accessible always.
APEP is set to 0 during
H_RESET and is unaffected by
S_RESET and the STOP bit.
10-8
APDW
MII Auto-Poll Dwell Time. APDW
determines the dwell time be-
tween MII Management Frames
accesses
when
turned on. See Table 41.
Auto-Poll
is
Read/Write accessible always.
APDW is set to 100h after
H_RESET and is unaffected by
S_RESET and the STOP bit.
7
DANAS
Disable Auto-Negotiation Auto
Setup. When DANAS is set, the
Am79C971 controller after a
H_RESET or S_RESET will re-
main dormant and not automati-
cally startup the Auto-Negotiation
section or the enhanced automat-
ic port selection section. Instead,
the Am79C971 controller will wait
for the software driver to setup
the Auto-Negotiation portions of
the device. The automatic port
selection for Am79C971 control-
ler will resemble the Pcnet-PCI II
controller. The MII programming
in BCR33 and BCR34 is still valid.
The Am79C971 controller will not
generate
any
frames unless Auto-Poll is en-
abled.
management
Read/write accessible always.
DANAS is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
6
XPHYRST
External PHY Reset. When XPH-
YRST is set, the Am79C971 con-
troller after an H_RESET or
S_RESET will issue an MII man-
agement frames that will reset the
external PHY. This bit is needed
when there is no way to guaran-
tee the state of the external PHY.
This bit must be reprogrammed
after every H_RESET.
Read/Write accessible always.
XPHYRST is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYRST is only valid when the
internal Network Port Manager is
scanning for a network port.
5
XPHYANE
External PHY Auto-Negotiation
Enable. This bit will force the ex-
ternal PHY into enabling Auto-
Negotiation. When set to 0 the
Am79C971 controller will send a
MII management frame disabling
Auto-Negotiation.
Read/Write accessible always.
XPHYANE is set to 0 by
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYANE is only valid when the
internal Network Port Manager is
scanning for a network port.
4
XPHYFD
External PHY Full Duplex. When
set, this bit will force the external
PHY into full duplex when Auto-
Negotiation is not enabled.
Read/Write accessible always.
XPHYFD
is
set
H_RESET, and is unaffected by
S_RESET and the STOP bit.
XPHYFD is only valid when the
internal Network Port Manager is
scanning for a network port.
to
0
by
3
XPHYSP
External PHY Speed. When set,
this bit will force the external PHY
into 100 Mbps mode when Auto-
Negotiation is not enabled.
Read/Write accessible always.
XPHYSP
is
set
H_RESET, and is unaffected by
S_RESET and the STOP bit.
XPHYSP is only valid when the
internal Network Port Manager is
scanning for a network port.
to
0
by
2
MII
μ
L
Media Independent Interface for
Micro Linear 6692. When set, this
Table 41.
APDW Values
Auto-Poll
Dwell Time
Continuous (26
μ
s @ 2.5 MHz)
Every 128 MDC cycles (103
μ
s @ 2.5 MHz)
Every 256 MDC cycles (206
μ
s @ 2.5 MHz)
Every 512 MDC cycles (410
μ
s @ 2.5 MHz)
Every 1024 MDC cycles (819
μ
s @ 2.5 MHz)
Every 2048 MDC cycles (1640
μ
s @ 2.5 MHz)
Reserved
APDW
000
001
010
011
100
101
110-111