Am79C971
119
13
RES
Reserved location. Read and
written as zero.
12
MISSM
Missed Frame Mask. If MISSM is
set, the MISS bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
MISSM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
11
MERRM
Memory Error Mask. If MERRM
is set, the MERR bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
MERRM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
10
RINTM
Receive Interrupt Mask. If RINTM
is set, the RINT bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
9
TINTM
Transmit
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Interrupt
Mask.
If
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
8
IDONM
Initialization
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Done
Mask.
If
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
7
RES
Reserved location. Read and
written as zeros.
6
DXSUFLO
Disable Transmit Stop on Under-
flow error.
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C971 controller gracefully
recovers from an UFLO error. It
scans the transmit descriptor ring
until it finds the start of a new
frame and starts a new transmis-
sion.
Read/Write accessible always.
DXSUFLO
is
H_RESET or S_RESET and is
not affected by STOP.
cleared
by
5
LAPPEN
Look Ahead Packet Processing
Enable. When set to a 1, the
LAPPEN bit will cause the
Am79C971 controller to generate
an interrupt following the descrip-
tor write operation to the first buff-
er of a receive frame. This
interrupt will be generated in ad-
dition to the interrupt that is gen-
erated following the descriptor
write operation to the last buffer
of a receive packet. The interrupt
will be signaled through the RINT
bit of CSR0.
Setting LAPPEN to a 1 also en-
ables the Am79C971 controller to
read the STP bit of receive de-
scriptors. The Am79C971 con-
troller
will
use
information to determine where it
should begin writing a receive
packet
’
s data. Note that while in
this mode, the Am79C971 con-
troller can write intermediate
packet data to buffers whose de-
scriptors do not contain STP bits
set to 1. Following the write to the
last descriptor used by a packet,
the Am79C971 controller will
scan through the next descriptor
entries to locate the next STP bit
that is set to a 1. The Am79C971
controller will begin writing the
next packets data to the buffer
pointed to by that descriptor.
the
STP
Note that because several de-
scriptors may be allocated by the
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain