參數(shù)資料
型號(hào): AM79C971VCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
中文描述: 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝: TQFP-176
文件頁(yè)數(shù): 19/265頁(yè)
文件大小: 3190K
代理商: AM79C971VCW
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Am79C971
19
INTA
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, EXDINT, IDON,
JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT,
SINT, SLPINT, TINT, TXSTRT, UINT, MCCIINT, MC-
CINT, MPDTINT, MAPINT, MREINT, and STINT. Each
status flag has either a mask or an enable bit which al-
lows for suppression of INTA assertion. Table 1 shows
the flag meanings.
Output
By default INTA is an open-drain output. For applica-
tions that need a high-active edge-sensitive interrupt
signal, the INTA pin can be configured for this mode by
setting INTLEVEL (BCR2, bit 7) to 1.
When RST is active, INTA is the output for NAND tree
testing
.
IRDY
Initiator Ready
IRDY indicates the ability of the initiator of the transac-
tion to complete the current data phase. IRDY is used
in conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
Input/Output
When the Am79C971 controller is a bus master, it as-
serts IRDY during all write data phases to indicate that
valid data is present on AD[31:0]. During all read data
phases, the device asserts IRDY to indicate that it is
ready to accept the data.
When the Am79C971 controller is the target of a trans-
action, it checks IRDY during all write data phases to
determine if valid data is present on AD[31:0]. During
all read data phases, the device checks IRDY to deter-
mine if the initiator is ready to accept the data.
When RST is active, IRDY is an input for NAND tree
testing
.
PAR
Parity
Parity is even parity across AD[31:0] and C/BE[3:0].
When the Am79C971 controller is a bus master, it gen-
erates parity during the address and write data phases.
It checks parity during read data phases. When the
Am79C971 controller operates in slave mode, it checks
parity during every address phase. When it is the target
of a cycle, it checks parity during write data phases and
it generates parity during read data phases.
Input/Output
When RST is active, PAR is an input for NAND tree
testing
.
Table 1.
Interrupt Flags
Name
BABL
Description
Babble
Excessive
Deferral
Initialization
Done
Jabber
Memory Error
Missed Frame
Missed Frame
Count Over-
flow
Magic Packet
Interrupt
Receive
Collision Count
Overflow
Receive
Interrupt
Sleep Interrupt CSR5, bit 8
System Error
Transmit
Interrupt
Transmit Start
User Interrupt
Internal MII
Management
Command
Complete
Interrupt
MII
Management
Command
Complete
Interrupt
MII PHY Detect
Transition
Interrupt
Mask Bit
CSR3, bit 14
Interrupt Bit
CSR0, bit 14
EXDINT
CSR5, bit 6
CSR5, bit 7
IDON
CSR3, bit 8
CSR0, bit 8
JAB
MERR
MISS
CSR4, bit 0
CSR3, bit 11
CSR3, bit 12
CSR4, bit 1
CSR0, bit 11
CSR0, bit 12
MFCO
CSR4, bit 8
CSR4, bit 9
MPINT
CSR5, bit 3
CSR5, bit 4
RCVCCO
CSR4, bit 4
CSR4, bit 5
RINT
CSR3, bit 10
CSR0, bit 10
SLPINT
SINT
CSR5, bit 9
CSR5, bit 11
CSR5, bit 10
TINT
CSR3, bit 9
CSR0, bit 9
TXSTRT
UINT
CSR4, bit 2
CSR4, bit 7
CSR4, bit 3
CSR4, bit 6
MCCIINT
CSR7, bit 2
CSR7, bit 3
MCCINT
CSR7, bit 4
CSR7, bit 5
MPDTINT
CSR7, bit 0
CSR7, bit 1
Name
Description
MII Auto-Poll
Interrupt
MII
Management
Frame Read
Error Interrupt
Software Timer
Interrupt
Mask Bit
Interrupt Bit
MAPINT
CSR7, bit 6
CSR7, bit 7
MREINT
CSR7, bit 8
CSR7, bit 9
STINT
CSR7, bit 10
CSR7, bit 11
Table 1.
Interrupt Flags
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