參數(shù)資料
型號(hào)： AM79C960KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： PCnetTM-ISA Single-Chip Ethernet Controller
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁(yè)數(shù)： 79/127頁(yè)
文件大?。?/td> 814K
代理商： AM79C960KCW
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P R E L I M I N A R Y
AMD
1-421
Am79C960
buffer, it must not change any
field in the descriptor entry.
ERR is the OR of FRAM, OFLO,
CRC, or BUFF. ERR is written by
the PCnet-ISA controller.
FRAMING ERROR indicates
that the incoming frame con-
tained a non-integer multiple of
eight bits and there was an FCS
error. If there was no FCS error
on the incoming frame, then
FRAM will not be set even if there
was a non integer multiple of
eight bits in the frame. FRAM is
not valid in internal loopback
mode. FRAM is valid only when
ENP is set and OFLO is not.
FRAM is written by the PCnet-
ISA controller.
OVERFLOW error indicates that
the receiver has lost all or part of
the incoming frame, due to an in-
ability to store the frame in a
memory buffer before the inter-
nal FIFO overflowed. OFLO is
valid only when ENP is not set.
OFLO is written by the PCnet-
ISA controller.
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is written by
the PCnet-ISA controller.
BUFFER ERROR is set any time
the PCnet-ISA controller does
not own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
1)
The OWN bit of the next
buffer is zero.
2) FIFO overflow occurred
before the PCnet-ISA
controller polled the next
descriptor.
If a Buffer Error occurs, an Over-
flow Error may also occur
internally in the FIFO, but will not
be reported in the descriptor
status entry unless both BUFF
and OFLO errors occur at the
same time. BUFF is written by
the PCnet-ISA controller.
START OF PACKET indicates
that this is the first buffer used by
the PCnet-ISA controller for this
frame. It is used for data chaining
buffers. STP is written by the
PCnet-ISA controller.
14
ERR
13
FRAM
12
OFLO
11
CRC
10
BUFF
9
STP
8
ENP
END OF PACKET indicates that
this is the last buffer used by the
PCnet-ISA controller for this
frame. It is used for data chaining
buffers. If both STP and ENP are
set, the frame fits into one buffer
and there is no data chaining.
ENP is written by the PCnet-ISA
controller.
The HIGH ORDER 8 address
bits of the buffer pointed to by this
descriptor. This field is written by
the host and is not changed by
the PCnet-ISA controller.
7-0
HADR
RMD2
Bit
Name
Description
15-12 ONES
MUST BE ONES. This field is
written by the host and un-
changed by the PCnet-ISA
controller.
BUFFER BYTE COUNT is the
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length
of the buffer. This field is written
by the host and is not changed by
the PCnet-ISA controller.
11-0
BCNT
RMD3
Bit
Name
Description
15-12
11-0
RES
MCNT
RESERVED and read as zeros.
MESSAGE BYTE COUNT is the
length in bytes of the received
message, expressed as an un-
signed binary integer. MCNT is
valid only when ERR is clear and
ENP is set. MCNT is written by
the PCnet-ISA controller and
cleared by the host.
Transmit Descriptors
The Transmit Descriptor Ring Entries (TDREs) are com-
posed of 4 transmit message fields (TMD0-3). Together
they contain the following information:
I
The address of the actual message data buffer in
user or host memory.
I
The length of the message buffer.
I
Status information indicating the condition of the
buffer. The eight most significant bits of TMD1
(TMD1[15:8]) are collectively termed the STATUS
of the transmit descriptor.
相關(guān)PDF資料
PDF描述
AM79C961AKCW PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA
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