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參數(shù)資料
| 型號： | AM79C960KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 33/127頁 |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KCW |
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P R E L I M I N A R Y
AMD
1-375
Am79C960
dresses. This means that the software must clear the
descriptor own bits and reset its descriptor ring pointers
before the restart of the PCnet-ISA controller. The
reload of descriptor base addresses is performed in the
LANCE only after initialization, so a restart of the
LANCE without initialization leaves the LANCE pointing
at the same descriptor locations as before the restart.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4 words
(8 bytes).
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT bit
in CSR0), the PCnet-ISA controller reads the user-de-
fined base address for the transmit and receive
descriptor rings, which must be on an 8-byte boundary,
as well as the number of entries contained in the de-
scriptor rings. By default, a maximum of 128 ring entries
is permitted when utilizing the initialization block, which
uses values of TLEN and RLEN to specify the transmit
and receive descriptor ring lengths. However, the ring
lengths can be manually defined (up to 65535) by writing
the transmit and receive ring length registers
(CSR76,78) directly.
Each ring entry contains the following information:
I
The address of the actual message data buffer
in user or host memory
I
The length of the message buffer
I
Status information indicating the condition of
the buffer
Receive descriptor entries are similar (but not identical)
to transmit descriptor entries. Both are composed of four
registers, each 16 bits wide for a total of 8 bytes.
To permit the queuing and de-queuing of message buff-
ers, ownership of each buffer is allocated to either the
PCnet-ISA controller or the host. The OWN bit within the
descriptor status information, either TMD or RMD (see
section on TMD or RMD), is used for this purpose.
“Deadly Embrace” conditions are avoided by the owner-
ship mechanism. Only the owner is permitted to
relinquish ownership or to write to any field in the
descriptor entry. A device that is not the current owner of
a descriptor entry cannot assume ownership or change
any field in the entry.
Descriptor Ring Access Mechanism
At initialization, the PCnet-ISA controller reads the base
address of both the transmit and receive descriptor rings
into CSRs for use by the PCnet-ISA controller during
subsequent operation.
When transmit and receive functions begin, the base
address of each ring is loaded into the current descriptor
address registers and the address of the next descriptor
entry in the transmit and receive rings is computed and
loaded into the next descriptor address registers.
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| AM79C961AKCW | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKC | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961A | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AKIW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
| AM79C961AVCW | PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C961 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
| AM79C961A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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