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參數(shù)資料
| 型號： | AM79C960KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 61/127頁 |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KCW |
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P R E L I M I N A R Y
AMD
1-403
Am79C960
2
STOP
STOP assertion disables the chip
from all external activity. The chip
remains inactive until either
STRT or INIT are set. If STOP,
STRT and INIT are all set to-
gether, STOP will override STRT
and INIT.
STOP is set by writing a “1” or by
RESET. Writing a “0” has no ef-
fect. STOP is cleared by setting
either STRT or INIT.
STRT
assertion
PCnet-ISA controller to send and
receive frames, and perform
buffer management operations.
Setting STRT clears the STOP
bit. If STRT and INIT are set to-
gether, PCnet-ISA controller
initialization will be performed
first.
STRT is set by writing a “1”. Writ-
ing a “0” has no effect. STRT is
cleared by RESET or by setting
the STOP bit.
INIT
assertion
PCnet-ISA controller to begin the
initialization procedure which
reads in the initialization block
from memory. Setting INIT clears
the STOP bit. If STRT and INIT
are set together, PCnet-ISA con-
troller
initialization
performed first. INIT is not
cleared when the initialization se-
quence has completed.
INIT is set by writing a “1”. Writing
a “0” has no effect. INIT is cleared
by RESET or by setting the
STOP bit.
1
STRT
enables
0
INIT
enables
will
be
CSR1: IADR[15:0]
Bit
Name
Description
15-0 IADR [15:0]
Lower address of the Initializa-
tion address register. Bit location
0 must be zero. Whenever this
register is written, CSR16 is up-
dated with CSR1’s contents.
Read/Write
accessible
when the STOP bit in CSR0 is
set. Unaffected by RESET.
only
CSR2: IADR[23:16]
Bit
Name
Description
15-8
RES
Reserved locations. Read and
written as zero.
7-0 IADR [23:16]
Upper 8 bits of the address of the
Initialization Block. Bit locations
15-8 must be written with zeros.
Whenever this register is written,
CSR17 is updated with CSR2’s
contents.
Read/Write
accessible
when the STOP bit in CSR0 is
set. Unaffected by RESET.
only
CSR3: Interrupt Masks and Deferral Control
Bit
Name
Description
15
RES
Reserved location. Written as
zero and read as undefined.
Babble Mask. If BABLM is set,
the BABL bit in CSR0 will be
masked and will not set INTR flag
in CSR0.
BABLM is cleared by RESET and
is not affected by STOP.
Reserved location. Written as
zero and read as undefined.
Missed Frame Mask. If MISSM is
set, the MISS bit in CSR0 will be
masked and will not set INTR flag
in CSR0.
MISSM is cleared by RESET and
is not affected by STOP.
Memory Error Mask. If MERRM
is set, the MERR bit in CSR0 will
be masked and will not set INTR
flag in CSR0.
MERRM is cleared by RESET
and is not affected by STOP.
Receive
Interrupt
RINTM is set, the RINT bit in
CSR0 will be masked and will not
set INTR flag in CSR0.
RINTM is cleared by RESET and
is not affected by STOP.
Transmit Interrupt Mask. If
TINTM is set, the TINT bit in
CSR0 will be masked and will not
set INTR flag in CSR0.
TINTM is cleared by RESET and
is not affected by STOP.
Initialization Done Mask. If
IDONM is set, the IDON bit in
CSR0 will be masked and will not
set INTR flag in CSR0.
IDONM is cleared by RESET and
is not affected by STOP.
Reserved locations. Written as
zero and read as undefined.
14
BABLM
13
RES
12
MISSM
11
MERRM
10
RINTM
Mask.
If
9
TINTM
8
IDONM
7-5
RES
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