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參數(shù)資料
| 型號(hào)： | AM79C960KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-ISA Single-Chip Ethernet Controller |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 36/127頁(yè) |
| 文件大?。?/td> | 814K |
| 代理商： | AM79C960KCW |
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P R E L I M I N A R Y
AMD
1-378
Am79C960
If the PCnet-ISA controller does own the second TDTE
in a chain, it will gradually empty the contents of the first
buffer (as the bytes are needed by the transmit opera-
tion), perform a single-cycle DMA transfer to update the
status (reset the OWN bit in TMD1) of the first
descriptor, and then it may perform one data DMA ac-
cess on the second buffer in the chain before executing
another lookahead operation. (i.e. a lookahead to the
third descriptor.)
The PCnet-ISA controller can queue up to two packets
in the transmit FIFO. Call them packet “X” and packet
“Y”, where “Y” is after “X”. Assume that packet “X” is
currently being transmitted. Because the PCnet-ISA
controller can perform lookahead data transfer over an
ENP, it is possible for the PCnet-ISA controller to update
a TDTE in a buffer belonging to packet “Y” while packet
“X” is being transmitted if packet “Y” uses data chaining.
This operation will result in non-sequential TDTE ac-
cesses as packet “X” completes transmission and the
PCnet-ISA controller writes out its status, since packet
“X”’s TDTE is before the TDTE accessed as part of the
lookahead data transfer from packet “Y”.
This should not cause any problem for properly written
software which processes buffers in sequence, waiting
for ownership before proceeding.
If an error occurs in the transmission before all of the
bytes of the current buffer have been transferred, then
TMD2 and TMD1 of the current buffer will be written; in
that case, data transfers from the next buffer will not
commence. Instead, following the TMD2/TMD1 update,
the PCnet-ISA controller will go to the next transmit
packet, if any, skipping over the rest of the packet which
experienced an error, including chained buffers.
This is done by returning to the polling microcode where
it will immediately access the next descriptor and find
the condition OWN = 1 and STP = 0 as described earlier.
In that case, the PCnet-ISA controller will reset the own
bit for this descriptor and continue in like manner until a
descriptor with OWN = 0 (no more transmit packets in
the ring) or OWN = 1 and STP = 1 (the first buffer of a
new packet) is reached.
At the end of any transmit operation, whether successful
or with errors, and the completion of the descriptor up-
dates, the PCnet-ISA controller will always perform
another poll operation. As described earlier, this poll op-
eration will begin with a check of the current RDTE,
unless the PCnet-ISA controller already owns that de-
scriptor. Then the PCnet-ISA controller will proceed to
polling the next TDTE. If the transmit descriptor OWN bit
has a zero value, then the PCnet-ISA controller will re-
sume poll time count incrementation. If the transmit
descriptor OWN bit has a value of ONE, then the
PCnet-ISA controller will begin filling the FIFO with
transmit data and initiate a transmission. This end-of-
operation poll avoids inserting poll time counts between
successive transmit packets.
Whenever the PCnet-ISA controller completes a trans-
mit packet (either with or without error) and writes the
status information to the current descriptor, then the
TINT bit of CSR0 is set to indicate the completion of a
transmission. This causes an interrupt signal if the IENA
bit of CSR0 has been set and the TINTM bit of CSR3
is reset.
Receive Descriptor Table Entry (RDTE)
If the PCnet-ISA controller does not own both the cur-
rent and the next Receive Descriptor Table Entry, then
the PCnet-ISA controller will continue to poll according
to the polling sequence described above. If the receive
descriptor ring length is 1, there is no next descriptor,
and no look ahead poll will take place.
If a poll operation has revealed that the current and the
next RDTE belongs to the PCnet-ISA controller, then
additional poll accesses are not necessary. Future poll
operations will not include RDTE accesses as long as
the PCnet-ISA controller retains ownership to the cur-
rent and the next RDTE.
When receive activity is present on the channel, the
PCnet-ISA controller waits for the complete address of
the message to arrive. It then decides whether to accept
or reject the packet based on all active addressing
schemes. If the packet is accepted the PCnet-ISA con-
troller checks the current receive buffer status register
CRST (CSR40) to determine the ownership of the cur-
rent buffer.
If ownership is lacking, then the PCnet-ISA controller
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the PCnet-ISA
controller has no buffer in which to store the incoming
message. The MISS bit will be set in CSR0 and an inter-
rupt will be generated if IENA = 1 (CSR0) and
MISSM = 0 (CSR3). Another poll of the current RDTE
will not occur until the packet has finished.
If the PCnet-ISA controller sees that the last poll (either
a normal poll or the last-ditch effort described in the
above paragraph) of the current RDTE shows valid own-
ership, then it proceeds to a poll of the next RDTE.
Following this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive descrip-
tor, the PCnet-ISA controller will continue to perform
receive data DMA transfers to the first buffer, using
burst-cycle DMA transfers. If the packet length exceeds
the length of the first buffer, and the PCnet-ISA control-
ler does not own the second buffer, ownership of the
current descriptor will be passed back to the system by
writing a zero to the OWN bit of RMD1 and status will be
written indicating buffer (BUFF = 1) and possibly over-
flow (OFLO = 1) errors.
If the packet length exceeds the length of the first (cur-
rent) buffer, and the PCnet-ISA controller does own the
second (next) buffer, ownership will be passed back to
the system by writing a zero to the OWN bit of RMD1
when the first buffer is full. Receive data transfers to the
second buffer may occur before the PCnet-ISA control-
ler proceeds to look ahead to the ownership of the third
buffer. Such action will depend upon the state of the
FIFO when the status has been updated on the first de-
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| AM79C961AKCW | PCnet ⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C961 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C961 - PCnet-ISA+ Jumperless Single-Chip Ethernet Controller for ISA |
| AM79C961/AM79C961A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF) |
| AM79C961A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-ISA II Jumperless, Full Duplex Single-Chip Ethernet Controller for ISA |
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