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參數(shù)資料
| 型號(hào)： | AM79C940 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問(wèn)控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁(yè)數(shù)： | 65/122頁(yè) |
| 文件大小： | 914K |
| 代理商： | AM79C940 |
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AMD
65
Am79C940
threshold is reached. When us-
ing the burst mode,
TDTREQ
will
not be de-asserted until only a
single write cycle can be per-
formed. See the FIFO Sub-sys-
tem section for additional details.
Receive FIFO
RCVFW
controls
RDTREQ
is asserted in relation
to the number of bytes available
in the RCVFIFO. RCVFW speci-
fies the number of bytes which
must be present (once the packet
has been verified as a non-runt),
before the
RDTREQ
is asserted.
Note however that in order for
RDTREQ
to be activated for a
new frame, at least 64-bytes
must have been received. This
effectively avoids reacting to re-
ceive frames which are runts or
suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature (RPA in
Receive Frame Control) is en-
abled, the
RDTREQ
pin will be
activated as soon as either
64-bytes are received, or a com-
plete valid receive frame is de-
tected (regardless of length).
RCVFW is set to a value of 10 (64
bytes) after hardware or software
reset.
Receive FIFO Watermarks
Bit 5-4
RCVFW
[1–0]
Watermark.
the
point
RCVFW [1–0]
Bytes
00
16
01
32
10
64
11
XX
The RCVFW value will only be
updated when the RCVFWU bit
is set.
Transmit FIFO Watermark Up-
date. Allows update of the Trans-
mit FIFO Watermark bits. The
XMTFW can be written at any
point, and will be read back as
written. However, the new value
in the XMTFW bits will be ignored
until XMTFWU is set (or the
transmit path is reset due to a
Bit 3
XMTFWU
retry failure). The recommended
procedure to change the XMTFW
is to write the new value with
XMTFWU set, in a single write
cycle. The XMTFIFO should be
empty and all transmit activity
complete before attempting a
watermark update, since the
XMTFIFO will be reset to allow
the new pointer values to be
loaded. It is recommended that
the transmitter be disabled by
clearing
the
XMTFWU will be cleared by the
MACE device after the new
XMTFW value has been loaded,
or by activation of the
RESET
pin
or SWRST bit.
Receive FIFO Watermark Up-
date. Allows update of the Re-
ceive FIFO Watermark bits. The
RCVFW bits can be written at
any point, and will read back as
written. However, the new value
in the RCVFW bits will be ignored
until RCVFWU is set. The recom-
mended procedure to change the
RCVFW is to write the new value
with RCVFWU set, in a single
write cycle. The RCVFIFO
should be empty before attempt-
ing a watermark update, since
the RCVFIFO will be reset to al-
low the new pointer values to be
loaded. It is recommended that
the receiver be disabled by clear-
ing the ENRCV bit. RCVFWU will
be cleared by the MACE device
after the new RCVFW value has
been loaded, or by activation of
the
RESET
pin or SWRST bit.
Transmit Burst. When set, the
transmit burst mode is selected.
The behavior of the Transmit
FIFO high watermark, and hence
the de-assertion of
TDTREQ
, will
be modified.
TDTREQ
will be
deasserted if there are only two
bytes of space available in the
XMTFIFO (so that a full word
write can still occur) or if four
bytes of space exist and the
EOF
pin is asserted by the host.
ENXMT
bit.
Bit 2
RCVFWU
Bit 1
XMTBRST
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C940JCW | Media Access Controller for Ethernet (MACE) |
| AM79C940KCW | Media Access Controller for Ethernet (MACE) |
| AM79C960 | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C940_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940-16/25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| AM79C940-16JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940AVC | 制造商:AMD 功能描述:79C940 AMD'94 SMT N6E2A |
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