- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C940 (Advanced Micro Devices, Inc.) Media Access Controller for Ethernet (MACE) PDF資料下載
參數(shù)資料
| 型號： | AM79C940 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁數(shù)： | 49/122頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁
AMD
49
Am79C940
Depending on the bus latency of the system, XMTFW
can be set to ensure that the Transmit FIFO does not
underflow before more data is written into the FIFO.
When the entire frame is in the FIFO,
TDTREQ
will re-
main asserted if sufficient bytes remain empty. The
default value of XMTFW is 64 bytes after hardware or
software reset. Note that if the XMTFW is set below the
64 byte limit, the transmit latency for the host to service
the MACE device is effectively increased, since
TDTREQ
will occur earlier in the transmit sequence and
more bytes will be present in the Transmit FIFO when
the
TDTREQ
is de-asserted.
The transmit operation of the MACE device can be
halted at any time by clearing the ENXMT bit (bit 1) in the
MAC Configuration Control register. Note that any com-
plete transmit frame that is in the Transmit FIFO and is
currently in progress will complete, prior to the transmit
function halting. Transmit frames in the FIFO which
have not commenced will not be started. Transmit
frames which have commenced but which have not
been fully transferred into the Transmit FIFO will be
aborted, in one of two ways. If less than 544 bits
(68 bytes) have been transmitted onto the network, the
transmission will be terminated immediately, generating
a runt packet which can be deleted at the receiving sta-
tion. If greater than 544 bits have been transmitted, the
messages will have the current CRC inverted and ap-
pended at the next byte boundary, to guarantee an error
is detected at the receiving station. This feature ensures
that packets will not be generated with potential unde-
tected data corruption. An explanation of the 544 bit
derivation appears in the “Automatic Pad Generation”
section.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble) permitting
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed, with no software inter-
vention from the host system.
APAD XMT = 1 enables the automatic padding feature.
The pad is placed between the LLC Data field and FCS
field in the 802.3 frame. The FCS is always added if
APAD XMT = 1, regardless of the state of DXMTFCS.
The transmit frame will be padded by bytes with the
value of 00h. The default value of APAD XMT will enable
auto pad generation after hardware or software reset.
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes en-
capsulated in the packet (length field as defined in the
IEEE 802.3 standard). The length value contained in the
message is not used by the MACE device to compute
the actual number of pad bytes to be inserted. The
MACE chip will append pad bytes dependent on the ac-
tual number of bits transmitted onto the network. Once
the last data byte of the frame has completed, prior to
appending the FCS, the MACE device will check to en-
sure that 544 bits have been transmitted. If not, pad
bytes are added to extend the frame size to this value,
and the FCS is then added.
Preamble
1010....1010
SFD
10101011
Dest
Addr
Srce
Addr
Length
LLC
Data
Pad
FCS
56
Bits
8
Bits
6
Bytes
6
Bytes
2
Bytes
46—1500
Bytes
4
Bytes
16235C-7
IEEE 802.3 Format Data Frame
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble,
including FCS)
64 bytes
512 bits
Preamble/SFD size
8 bytes
64 bits
FCS size
4 bytes
32bits
To be classed as a minimum size frame at the receiver,
the transmitted frame must contain:
Preamble
+
(Min Frame Size + FCS) bits
At the point that FCS is to be appended, the transmitted
frame should contain:
Preamble
64
+
+
(Min Frame Size - FCS) bits
(512
-
32) bits
A minimum length transmit frame from the MACE
device will therefore be 576 bits, after the FCS is
appended.
The Ethernet specification makes no use of the LLC pad
field, and assumes that minimum length messages will
be at least 64 bytes in length.
相關PDF資料 |
PDF描述 |
|---|---|
| AM79C940JCW | Media Access Controller for Ethernet (MACE) |
| AM79C940KCW | Media Access Controller for Ethernet (MACE) |
| AM79C960 | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C940_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940-16/25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| AM79C940-16JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940AVC | 制造商:AMD 功能描述:79C940 AMD'94 SMT N6E2A |
發(fā)布緊急采購，3分鐘左右您將得到回復。