- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C940 (Advanced Micro Devices, Inc.) Media Access Controller for Ethernet (MACE) PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C940 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 媒體訪問(wèn)控制器（MACE發(fā)生以太網(wǎng)） |
| 文件頁(yè)數(shù)： | 29/122頁(yè) |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)當(dāng)前第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)
AMD
29
Am79C940
FUNCTIONAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip
embodies the Media Access Control (MAC) and Physi-
cal Signaling (PLS) sub-layers of the 802.3 Standard.
The MACE device provides the IEEE defined Attach-
ment Unit Interface (AUI) for coupling to remote Media
Attachment Units (MAUs) or on-board transceivers.
The MACE device also provides a Digital Attachment In-
terface (DAI), by-passing the differential AUI interface.
The system interface provides a fundamental data con-
duit to and from an 802.3 network. The MACE device in
conjunction with a user defined DMA engine, provides
an 802.3 interface tailored to a specific application.
In addition, the MACE device can be combined with
similarly architected peripheral devices and a multi-
channel DMA controller, thereby providing the system
with access to multiple peripheral devices with a single
master interface to memory.
Network Interfaces
The MACE device can be connected to an 802.3 net-
work using any one of the AUI, 10 BASE-T, DAI and
GPSI network interfaces. The Attachment Unit Inter-
face (AUI) provides an IEEE compliant differential inter-
face to a remote MAU or an on-board transceiver. An
integrated 10BASE-T MAU provides a direct interface
for twisted pair Ethernet networks. The DAI port can
connect to local transceiver devices for 10BASE2,
10BASE-T or 10BASE-F connections. A General Pur-
pose Serial Interface (GPSI) is supported, which effec-
tively
bypasses
the
encoder/decoder, and allows direct access to/from the
integral 802.3 Media Access Controller (MAC) to pro-
vide support for external encoding/decoding schemes.
The interface in use is determined by the PORTSEL
[1–0] bits in the PLS Configuration Control register.
The EADI port does not provide network connectivity,
but allows an optional external circuit to assist in receive
packet accept/reject.
integrated
Manchester
System Interface
The MACE device is a slave register based peripheral.
All transfers to and from the device, including data, are
performed using simple memory or I/O read and write
commands. Access to all registers, including the Trans-
mit and Receive FIFOs, are performed with identical
read or write timing. All information on the system inter-
face is synchronous to the system clock (SCLK), which
allows simple external logic to be designed to interro-
gate the device status and control the network data flow.
The Receive and Transmit FIFOs can be read or written
by driving the appropriate address lines and asserting
CS
and R/
W
. An alternative FIFO access mechanism al-
lows the use of the
FDS
and the R/
W
lines, ignoring the
address lines (ADD
4–0
). The state of the R/
W
line in
conjunction with the
FDS
input determines whether the
Receive FIFO is read (R/
W
high) or the Transmit FIFO
written (R/
W
low). The MACE device system interface
permits interleaved transmit and receive bus transfers,
allowing the Transmit FIFO to be filled (primed) while a
frame is being received from the network and/or read
from the Receive FIFO.
In receive operation, the MACE device asserts Receive
Data Transfer Request (
RDTREQ
) when the FIFO con-
tains adequate data. For the first indication of a new re-
ceive frame, 64 bytes must be received, assuming
normal operation. Once the initial 64 byte threshold has
been reached,
RDTREQ
assertion and de-assertion is
dependent on the programming of the Receive FIFO
Watermark (RCVFW bits in the BIU Configuration Con-
trol register). The
RDTREQ
can be programmed to acti-
vate when there are 16, 32 or 64 bytes of data available
in the Receive FIFO. Enable Receive (ENRCV bit in
MAC Configuration Control register) must be set to as-
sert
RDTREQ
. If the Runt Packet Accept feature is in-
voked (RPA bit in User Test Register),
RDTREQ
will be
asserted for receive frames of less than 64 bytes on the
basis of internal and/or external address match only.
When RPA is set,
RDTREQ
will be asserted when the
entire frame has been received or when the initial 64
byte threshold has been exceeded. See the FIFO Sub-
Systems section for further details.
Note that the Receive FIFO may not contain 64 data
bytes at the time
RDTREQ
is asserted, if the automatic
pad stripping feature has been enabled (ASTRP RCV
bit in the Receive Frame Control register) and a mini-
mum length packet with pad is received. The MACE de-
vice will check for the minimum received length from the
network, strip the pad characters, and pass only the
data frame through the Receive FIFO.
If the Low Latency Receive feature is enabled (LLRCV
bit set in Receive Frame Control Register),
RDTREQ
will be asserted once a low watermark threshold has
been reached (12 bytes plus some additional synchroni-
zation time). Note that the system interface will there-
fore be exposed to potential disruption of the receive
frame due to a network condition (see the FIFO Sub-
System description for additional details).
In transmit operation, the MACE device asserts Trans-
mit Data Transfer Request (
TDTREQ
) dependent on the
programming of the Transmit FIFO Watermark
(XMTFW bits in the BIU Configuration Control register).
TDTREQ
will be permanently asserted when the Trans-
mit FIFO is empty. The
TDTREQ
can be programmed to
activate when there are 16, 32 or 64 bytes of space
available in the Transmit FIFO. Enable Transmit
(ENXMT bit in MAC Configuration Control register)
must be set to assert
TDTREQ
. Write cycles to the
Transmit FIFO will not return
DTV
if ENXMT is disabled,
and no data will be written. The MACE device will com-
mence the preamble sequence once the Transmit Start
Point (XMTSP bits in BIU Configuration Control regis-
ter) threshold is reached in the Transmit FIFO.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C940JCW | Media Access Controller for Ethernet (MACE) |
| AM79C940KCW | Media Access Controller for Ethernet (MACE) |
| AM79C960 | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KC | PCnetTM-ISA Single-Chip Ethernet Controller |
| AM79C960KCW | PCnetTM-ISA Single-Chip Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C940_00 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940-16/25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| AM79C940-16JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940-25JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C940AVC | 制造商:AMD 功能描述:79C940 AMD'94 SMT N6E2A |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。