參數(shù)資料
型號： AM79C930VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
中文描述： 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 39/161頁
文件大?。?/td> 691K
代理商： AM79C930VCW
P R E L I M I N A R Y
AMD
39
Am79C930
Pin 115: TXC
The TXC pin may be configured for input or output op-
eration according to the table below:
TXC input configuration is the reset default configura-
tion. This configuration allows an external transceiver to
control the clock that serves as the reference for the
transmit data. While in this configuration, the internal TX
state machine continues to operate with a reference
clock derived from a divided version of the CLKIN input.
Since the external TXC source is not driving the
Am79C930 device TX state machine, there exists a
synchronizing FIFO between the CRC generator and
the TXDATA pin that is used only in the TXC input mode.
This serial FIFO is 16 bits long and is used to allow for
slight mismatch between the internal TX state machine
reference clock and the external TXC input clock. It is
imperative in the TXC input mode that the Data Rate se-
lected with the Data Rate bits of TCR30 must match the
expected TXC clock rate from the transceiver. If these
rates do not match, then there is a risk of internal serial
FIFO error which, if it occurred, would be signaled
through the ATFU and ATFO interrupts of TCR11.
TXCIN
TCR30[3]
0
1
TXC Pin
Direction
O
I
TXC Pin
Value
TXC
NA
(result of internal divide of CLKIN)
reset default condition
Pin 118:
LFPE
The
LFPE
pin may be configured for input or output op-
eration according to the table below:
Note that a read of the LFPE bit (TIR0[1]) will always
yield the inverted logical sense of the current
LFPE
pin
value, regardless of pin configuration setting.
Note that the value of the LFPE bit (TIR0[1]) also affects
the value of the LFCLK pin.
LFPEEN
TCR13[6]
0
1
1
1
LFPE
TIR0[1]
X
0
1
1
CLKGT20
MIR9[7]
X
X
0
1
LFPE
Pin
Direction
I
O
O
O
LFPE
Pin
Value
NA
HIGH
LOW
LOW
LFCLK Pin
Value
LOW
LOW reset default condition
CLKIN
CLKIN
÷
2
Pin 120:
HFPE
The
HFPE
pin may be configured for input or output op-
eration according to the following table:
Note that a read of the HFPE bit (TIR0[0]) will always
yield the inverted logical sense of the current
HFPE
pin
value, regardless of pin configuration setting.
Note that the value of the HFPE bit (TIR0[0]) also affects
the value of the HFCLK pin.
HFPEEN
TCR13[5]
0
1
1
1
HFPE
TIR0[0]
X
0
1
1
CLKGT20
MIR9[7]
X
X
0
1
HFPE
Pin
Direction
I
O
O
O
HFPE
Pin
Value
NA
HIGH
LOW
LOW
HFCLK Pin
Value
LOW
LOW reset default condition
CLKIN
CLKIN
÷
2
Pin 122: RXPE
The
RXPE
pin may be configured for input or output op-
eration according to the following table:
Note that a read of the RXP bit (TIR0[2]) will always yield
the inverted logical sense of the current
RXPE
pin value,
regardless of pin configuration setting.
RXPELEN
TCR13[0]
0
1
1
RXP
TIR0[2]
X
0
1
RXPE
Pin
Direction
I
O
O
RXPE
Pin
Value
NA
HIGH
LOW
reset default condition
相關PDF資料
PDF描述
AM79C940VCW Media Access Controller for Ethernet (MACE)
AM79C940 Media Access Controller for Ethernet (MACE)
AM79C940JCW Media Access Controller for Ethernet (MACE)
AM79C940KCW Media Access Controller for Ethernet (MACE)
AM79C960 PCnetTM-ISA Single-Chip Ethernet Controller
相關代理商/技術參數(shù)
參數(shù)描述
AM79C940 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE)
AM79C940_00 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩)
AM79C940-16/25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
AM79C940-16JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C940-25JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
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