參數(shù)資料
型號: AM79C930VCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
中文描述: 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: TQFP-144
文件頁數(shù): 136/161頁
文件大小: 691K
代理商: AM79C930VCW
AMD
P R E L I M I N A R Y
136
Am79C930
ISA ACCESS
Parameter
Symbol
t
i
1
t
i
2
t
i
3
t
i
4
t
i
7
t
i
8
t
i
9
t
i
10
t
i
11
t
i
12
t
i
13
t
i
14
t
i
15
t
i
16
t
i
20
t
i
21
Parameter Description
LA[23:17] valid setup to BALE
BALE
to BALE
pulse width
LA[23:17] valid hold from BALE
LA[23:17] valid setup to
CMD
SA[16:0] valid setup to
CMD
CMD
to
CMD
pulse width
SA[16:0] valid setup to BALE
Data valid delay from
RCMD
Data valid setup to
WCMD
SA[16:0] valid hold from
CMD
CMD
to
CMD
pulse width
Data valid hold from
RCMD
Data valid hold from
WCMD
Data disabled from
RCMD
IOCHRDY
delay from
CMD
IOCHRDY
to IOCHRDY
pulse width
CMD
delay from IOCHRDY
BALE
delay from
CMD
Data valid delay from IOCHRDY
LA[23:17] valid hold from
CMD
AEN valid setup to
CMD
AEN valid hold from
CMD
AEN valid setup to BALE
Data enabled from
RCMD
Test Conditions
Min
60
25
12
80
25
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 4
6*T
CLKIN
20
Notes 2, 5, 6
Note 3
Note 1
Note 1
Note 2
Note 3
Note 2, 6
Notes 1, 7
Notes 5, 6, 7
53 X T
CLKIN
–75
20
55
0
20
20
60
0
130 +
53 X T
CLKIN
t
i
22
t
i
23
t
i
25
t
i
26
t
i
30
t
i
31
t
i
32
t
i
34
Notes 1, 7
Note 1
Note 7
Note 1
Note 1
Note 1
35
20
ns
ns
ns
ns
ns
ns
ns
ns
–T
CLKIN
–15
80
15
60
0
25
Notes 2, 4
110
Notes:
1.
CMD
= one of:
MEMR
,
MEMW
,
IOR
or
IOW
.
2.
RCMD
= one of:
MEMR
, or
IOR
.
3.
WCMD
= one of:
MEMW
, or
IOW
.
4. If no wait states are incurred.
5. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
FLASH and SRAM wait states set at “3.”
1
Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
Host performs ISA READ cycle immediately following completion of ISA WRITE cycle.
4
After completion of first embedded 80188 access to FLASH, posted ISA WRITE executes to SRAM;
ISA READ stycle is being held in wait state.
5
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6
After completion of second embedded 80188 access to FLASH, ISA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to ISA bus and wait state is exited.
6. Parameter is not included in production test.
7. Parameter only applies when IOCHRDY is deasserted.
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相關代理商/技術參數(shù)
參數(shù)描述
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