
SPRS550C
– OCTOBER 2009 – REVISED MARCH 2011
– Supports YCbCr422 Format (8-bit or 16-bit
– ARM Instructions - Little Endian
With Discrete Horizontal and Vertical Sync
– ARM Data – Configurable
Signals)
SDRC Memory Controller
– Generates Optical Black Clamping Signals
– 16/32-bit Memory Controller With 1G-Byte
– Built-in Digital Clamping and Black Level
Total Address Space
Compensation
– Double Data Rate (DDR2) SDRAM, mobile
– 10-bit to 8-bit A-law Compression Hardware
Double Data Rate (mDDR)SDRAM
– Supports up to 16K Pixels (Image Size) in
– SDRAM Memory Scheduler (SMS) and
Horizontal and Vertical Directions
Rotation Engine
System Direct Memory Access (sDMA)
General Purpose Memory Controller (GPMC)
Controller (32 Logical Channels With
– 16-bit Wide Multiplexed Address/Data Bus
Configurable Priority)
– Up to 8 Chip Select Pins With 128M-Byte
Comprehensive Power, Reset and Clock
Address Space per Chip Select Pin
Management
– Glueless Interface to NOR Flash, NAND
ARM CortexTM-A8 Memory Architecture
Flash (With ECC Hamming Code
– ARMv7 Architecture
Calculation), SRAM and Pseudo-SRAM
– In-Order, Dual-Issue, Superscalar
– Flexible Asynchronous Protocol Control for
Microprocessor Core
Interface to Custom Logic (FPGA, CPLD,
– ARM NEON Multimedia Architecture
ASICs, etc.)
– Over 2x Performance of ARMv6 SIMD
– Nonmultiplexed Address/Data Mode (Limited
2K-Byte Address Space)
– Supports Both Integer and Floating Point
SIMD
Test Interfaces
– Jazelle RCT Execution Environment
– IEEE-1149.1 (JTAG) Boundary-Scan
Architecture
Compatible
– Dynamic Branch Prediction with Branch
– Embedded Trace Macro Interface (ETM)
Target Address Cache, Global history buffer
65-nm CMOS technology
and 8 entry return stack
Packages:
– Embedded Trace Macrocell [ETM] support
– 491-pin BGA (17x17, 0.65mm pitch)
for Non_invasive Debug
[ZCN suffix]
– 16K-Byte instruction Cache (4-Way set-
with via channel array technology
associative)
– 484-pin PBGA (23x23, 1mm pitch)
– 16K-Byte Data Cache (4-Way
[ZER suffix]
Set-Associative)
Applications:
– 256K-Byte L2 Cache
– Single Board Computers
POWERVR SGX Graphics Accelerator
– Industrial and Home Automation
– Tile Based Architecture Delivering up to 10
– Digital Signage
MPoly/sec
– Point of Service
– Universal Scalable Shader Engine:
– Portable Media Player
Multi-threaded Engine Incorporating Pixel
– Portable Industrial
and Vertex Shader Functionality
– Transportation
– Industry Standard API Support: OpenGLES
– Navigation
1.1 and 2.0, OpenVG1.0
– Smart White Goods
– Fine Grained Task Switching, Load
– Digital TV
Balancing, and Power Management
– Digital Video Camera
– Programmable, High-Quality Image
Anti-Aliasing
– Gaming
Endianess
2
AM3517/05 Sitara ARM Microprocessor
Copyright
2009–2011, Texas Instruments Incorporated