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參數(shù)資料
| 型號： | AM30LV0064DJ40WGIT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology |
| 中文描述： | 8M X 8 FLASH 3V PROM, 35 ns, PBGA40 |
| 封裝： | 8 X 15 MM, 0.80 MM PITCH, FBGA-40 |
| 文件頁數(shù)： | 18/41頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | AM30LV0064DJ40WGIT |
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18
Am30LV0064D
Read Spare Area (50h)
The Read Spare Area command is similar to the Read
Data command, except that it only reads information
from the selected page 16 byte Spare Area (address
locations 512 through 527). After the command cycle
is used to write the Read Spare Area op-code to the
device, three address cycles are used to input the
starting address for the read operation. During the
Read Spare Area command cycle the SE# input must
be low.
Because the Read Spare Area operation only reads
the 16 byte spare area in the page, address bits
A7–A4 are don’t care. Address bits A22–A9 are used
to select the Page, and address bits A3–A0 are used
to select the starting byte within the Spare Area of the
Page. Upon the rising edge of the final WE# pulse
there is a 7 μs latency in which all 528 bytes of infor-
mation are transferred from the Flash array page to
the 528 byte Data Register. Following the data transfer
the internal address pointer will point to the byte se-
lected in the Spare Area. During the 7 μs data transfer
period the device will appear busy and the RY/BY#
signal or the status register may be used to monitor
the completion of the data transfer. Only the Reset and
Read Status commands are valid during the period
that the device is busy. Once the information has been
loaded into the Data Register, the Spare Area informa-
tion may be sequentially read with consecutive 50 ns
RE# pulses. Each RE# pulse will automatically ad-
vance the Spare Area column address by one. Once
the last column has been read, the page address will
automatically increment by one and the Data Register
will be updated with the new page after a 7 μs latency.
During the sequential read mode, the Spare Area En-
able input (SE#) must be low. This is necessary any
time the Spare Area is being read. In this operation,
the column address will advance from the selected
starting byte location to address 527 before the page
address is incremented. After the next page of infor-
mation is transferred to the Data Register, sequential
read operations will begin in the Data Register at ad-
dress location 512. Unlike the Read Data and Gapless
Read modes, the Read Spare Area operation requires
that the SE# input be asserted low prior to the com-
mand being issued to the device.
Figure 4. Read Spare Area
CE#
CLE
ALE
WE#
RE#
I/O7-0
SE#
RY/BY#
CMD
Start Address
Read Spare Area
Read Next Spare Area
Read Next Spare Area
Data Transfer
Data Transfer
Data Transfer
Read Spare Area (50h)
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