參數(shù)資料
型號(hào)： AM30LV0064DJ40WGIT
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： PROM
英文描述： 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology
中文描述： 8M X 8 FLASH 3V PROM, 35 ns, PBGA40
封裝： 8 X 15 MM, 0.80 MM PITCH, FBGA-40
文件頁(yè)數(shù)： 15/41頁(yè)
文件大小： 1067K
代理商： AM30LV0064DJ40WGIT
Am30LV0064D
15
DEVICE OPERATIONS
When the AMD Mass Storage Flash device powers
up, the command decoder is initialized to a wait for
command state. In order to perform any function, the
device must be programmed for the desired operation.
Specific commands must be issued to the device to
select one of the read modes, to input or program
data, to perform one of the block erase functions, or to
reset the device.
There are a number of commands available for read-
ing information from the UltraNAND Flash device.
These include Read Data to read out of the Flash ar-
ray, Gapless Read to read data in a special high
performance mode, Read Spare Area to read the 16
byte spare area in each page, Read ID to determine
the manufacturer and device ID, and Read Status to
check the device status.
Programming data into the Flash array is a two step
process and requires that two separate command se-
quences be performed. The data to be programmed
must first be loaded into the Data Registers using the
Input Data command sequence. After the data is
loaded the Page Program command is performed to
transfer the information from the Data Registers to the
Flash array.
Device erasure occurs on an 8 Kbyte block basis, with
each block in the device containing 16 pages and the
respective spare area for each page. During block
erase, the Flash device supports erase suspend and
erase resume to allow time critical tasks to be per-
formed. These time critical tasks can be to read or
program in a block that is not currently selected for
erasure.
The Flash device also supports a reset command se-
quence to reset the device and return it to the wait for
command state.
All of the commands and their functions supported by
the Flash device are described in the following
sub-sections with simplified timing diagrams included.
The timing diagrams are intended to illustrate the rela-
tionship of each of the control, status, and data signals
for each of the command sequences. Please refer to
the AC/DC Characteristics section for more complete
timing information.
In each of the simplified timing diagrams, the polling
period during device busy (RY/BY# = V
IL
) is not
shown. During device busy the system can poll the de-
vice internal status register or monitor the RY/BY# pin
to determine when the internal operation is complete.
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