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| 型號(hào)： | AM24LC21NA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大小： | 220K |
| 代理商： | AM24LC21NA |
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AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
Note:
Page write operations are limited to writing bytes
within a single physical page, regardless
of the
number of bytes actually being written. Physical
page boundaries start at addresses that are integer
multiples of the page buffer size (or ‘page size’) and
end at addresses that are integer multiples of [page
size - 1]. If a page write command attempts to write
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
9/13
across a physical page boundary, the result is that
the data wraps around to the beginning of the
current page (overwriting data previously stored
there), instead of being written to the next page as
might be expected. It is therefore necessary for the
application
software
to
operations that would attempt to cross a page
boundary.
prevent
page
write
P
S
T
O
P
A
C
K
A
C
K
A
C
K
S
S
T
A
R
T
Control
Byte
Word
Address
Data
VCLK
Bus activity
SDA Line
Bus activity
Master
Figure 4-1. Byte write
S
T
O
P
A
C
K
A
C
K
S
S
T
A
R
T
Control
Byte
Word
Address
Data(n)
VCLK
Bus activity
SDA Line
Bus activity
Master
A
C
K
A
C
K
A
C
K
Data(n+1)
Data(n+7)
P
Figure 4-2. Page write
5.0 Acknowledge polling
Since the device will not acknowledge during a
write cycle, this can be used to determine when the
cycle is complete (this feature can be used to
maximize bus throughput). Once the stop condition
for a write command has been issued from the
master, the device initiates the internally timed write
cycle. ACK polling can be initiated immediately.
This involves the master sending a start condition
followed by the control byte for a write command
(R/W = 0). If the device is still busy with the write
cycle, then no ACK will be returned. If the cycle is
complete, then the device will return the ACK and
the master can then
proceed with the next read or write command. See
Figure 5-1 for the flow diagram.
6.0 Write protection
When using the AM24LC21 in the bi-directional
Mode, the VCLK pin operates as the write protect
control pin. Setting VCLK high allows normal write
operations, while setting VCLK low prevents writing
to any location in the array. Connecting the VCLK
pin to VSS would allow the AM24LC21 to operate
as a serial ROM, although this configuration would
prevent using the device in the transmit-only mode.
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| AM24LC21S | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21SA | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
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