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| 型號(hào)： | AM24LC21NA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | AM24LC21NA |
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AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
T
F
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
8/13
SCL
SDA
IN
SDA
OUT
T
SU:STA
T
HD:STA
T
HD:STA
T
HD:DAT
T
SU:DAT
T
SU:STO
T
BUF
T
AA
T
AA
T
SP
T
LOW
T
HIGH
T
R
Figure 3-5. Bus timing data
3.1.6 Slave address
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit
device code
(1010
) for the AM24LC21, followed by
three 000 3 bits. The eighth bit of slave address
determines if the master device wants to read or
write to the AM24LC21 (Figure 3-6). The
AM24LC21 monitors the bus for its corresponding
slave address all the time. It generates an
acknowledge bit if the slave address was true and it
is not in a programming mode.
Operation Control code Chip select
Read
1010
Write
1010
START
W
1
0
/
R
000
000
A
Slave address
R/W
READ/WRITE
1
0
1
0
0
0
0
4.1 Byte Write
Figure 3-6. Control byte allocation
4.2 Page Write
The write control byte, word address and the first
data byte are transmitted to the AM24LC21 in the
same way as in a byte write. But instead of
generating a stop condition the master transmits up
to eight data bytes to the AM24LC21 which are
temporarily stored in the on-chip page buffer and
will be written into the memory after the master has
transmitted a stop condition. After the receipt of
each word, the three lower order address pointer
bits are internally incremented by one. The higher
order five bits of the word address remains constant.
Following the start signal from the master, the slave
address (4 bits), 000 (3 bits) and the R/W bit which
is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will fol-low
after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmit-ted by the master is the word address and
will be written into the address pointer of the
AM24LC21. After receiving another acknowledge
signal from the AM24LC21 the master device will
transmit the data word to be writ-ten into the
addressed memory location. The AM24LC21
acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this time the AM24LC21 will not
generate acknowledge signals (Figure 4-1). It is
required that VCLK be held at a logic high level in
order to program the device. This applies to byte
write and page write operation. Note that VCLK can
go low while the device is in its self-timed program
operation and not affect programming.
If the
master should transmit more than eight words prior
to generating the stop condition, the address
counter will roll over and the previously received
data will be overwritten. As with the byte write
operation, once the stop condition is received an
internal write cycle will begin (Figure 4-2). It is
required that VCLK be held at a logic high level in
order to program the device. This applies to byte
write and page write operation. Note that VCLK can
go low while the device is in its self-timed program
operation and not affect programming.
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PDF描述 |
|---|---|
| AM24LC21S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21SA | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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|---|---|
| AM24LC21S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
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