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| 型號(hào)： | AM24LC21NA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | AM24LC21NA |
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AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
3.0 Bi-directional mode
The AM24LC21 can be switched into the
bi-directional mode (see Figure 3-1) by applying a
valid high to low transition on the bi-directional
mode clock (SCL). When the device has been
switched into the bi-directional mode, the VCLK
input is disregarded, with the exception that a logic
high level is required to enable write capability. This
mode supports a two wire bi-directional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the
transmitter, and a device that receives data from
the bus is defined to be the receiver. The bus must
be con-trolled by a master device that generates
the bi-directional mode clock (SCL), controls
access to the bus and generates the START and
STOP conditions, while the AM24LC21 acts as the
slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated. Any high to
low transition on the SCL line will reset the count. If
it sees a pulse count of 128 on VCLK while the SCL
line is idle, it will revert back to the Transmit-Only
Mode, and transmit its contents starting with the
most significant bit in address 00h.(see Figure 3-1,
3-2)
Transmit
Only
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 0.0 Aug 10, 2002
6/13
3.1 Bi-directional mode bus characteristics
The following bus protoco
l
has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have
been defined (see Figure 3-3).
3.1.1 Bus not busy (A)
Both data and clock lines remain HIGH.
3.1.2 Start data transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START
condition.
3.1.3 STOP data transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition.
All operations must be ended with a STOP
condition.
MODE
SCL
SDA
VCLK
VCLK count =
1
2
Bi-directional
Recovery to Transmit-Only Mode
TVHZ
3
4
127
128
Bit8
(MSB of data in 00h)
Figure 3-1. Mode transition
MODE
SCL
SDA
VCLK
n < 128
VCLK count =
1
2
n
0
S
1
0
1
0
0
0
0
0
ACK
Transmit
Only Mode
Transition Mode with possibility to return to Transmit-Only Mode
Bi-directional
permanently
Figure 3-2. Successful Mode transition
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PDF描述 |
|---|---|
| AM24LC21S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21SA | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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|---|---|
| AM24LC21S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
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