參數(shù)資料
型號(hào)： AM24LC21NA
廠商： Electronic Theatre Controls, Inc.
元件分類： DRAM
英文描述： The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述： 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù)： 5/13頁(yè)
文件大?。?/td> 220K
代理商： AM24LC21NA
AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
Functional description
1.0 Overview
The AM24LC21 operates in two modes, the
transmit-only mode and the bi-directional mode.
There is a separate two wire protocol to support
each mode, each having a separate clock input and
sharing a common data line (SDA). The device
enters the Transmit-Only Mode upon power-up. In
this mode, the device transmits data bits on the
SDA pin in response to a clock signal on the VCLK
pin. The device will remain in this mode until a valid
high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the bi-directional mode. The
only way to switch the device back to the
transmit-only mode is to remove power from the
device.
2.1 Transmit-only mode
The device will power up in the transmit-only mode.
This mode supports a unidirectional two wire
protocol for trans-mission of the contents of the
memory array. This device requires that it be
initialized prior to valid data being sent in the
transmit-only mode (see Initialization Procedure,
Anachip Corp.
www.anachip.com.tw
Rev 0.0 Aug 10, 2002
5/13
below). In this mode, data is transmitted on the
SDA pin in 8 bit bytes, each followed by a ninth, null
bit (see Figure 2-1). The clock source for the
transmit-only mode is provided on the VCLK pin,
and a data bit is output on the rising edge on this
pin. The eight bits in each byte are transmitted most
significant bit first. Each byte within the memory
array will be output in sequence. When the last byte
in the memory array is transmitted, the output will
wrap around to the first location and continue. The
bi-directional mode clock (SCL) pin must be held
high for the device to remain in the transmit-only
mode.
2.2 Initialization procedure
After VCC has stabilized, the device will be in the
transmit-only mode. Nine clock cycles on the VCLK
pin must be given to the device for it to perform
internal synchronization. During this period, the
SDA pin will be in a high impedance state. On the
rising edge of the tenth clock cycle, the device will
output the first valid data bit which will be the most
significant bit of a byte. The device will power up at
an indeterminate byte address. (Figure 2-2).
SCL
SDA
VCLK
T
VHIGH
T
VLOW
T
VAA
T
VAA
B
IT
1(LSB)
N
ULL
B
IT
B
IT
7
B
IT
8(MSB)
Figure 2-1. Transmit only mode
SCL
SDA
VCLK
V
CC
T
VAA
T
VAA
B
IT
8
B
IT
7
11
10
9
8
2
1
T
VPU
H
IGH
I
MPEDANCE FOR
9
CLOCK CYCLES
Figure 2-2. Device initialization
相關(guān)PDF資料
PDF描述
AM24LC21S The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
AM24LC21SA The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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AM26C31CDB QUADRUPLE DIFFERENTIAL LINE DRIVERS
AM26C31I QUADRUPLE DIFFERENTIAL LINE DRIVERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM24LC21S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
AM24LC21SA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM
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