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| 型號(hào)： | AM24LC21NA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | AM24LC21NA |
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AM24LC21
(Preliminary)
Dual Mode, 1K-bits (128 x 8) 2-Wire Serial
EEPROM
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 0.0 Aug 10, 2002
10/13
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Next
Operation
Die Device
Acknowledg
(ACK = 0)
YES
No
Figure 5-1: Acknowledge polling flow
7.0 Read operation
Read operations are initiated in the same way as
write operations with the exception that the R/W bit
of the slave address is set to ‘1’. There are three
basic types of read operations: current address
read, random read and sequential read.
7.1 Current address read
The AM24LC21 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation)
was to address n, the next current address read
operation would access data from address n + 1.
Upon receipt of the slave address with R/W bit set
to ‘1’, the AM24LC21 issues an acknowledge and
transmits the eight bit data word. The master will
not acknowledge the transfer but does generate a
stop condition and the AM24LC21 discontinues
transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to
access any memory location in a random manner.
To perform this type of read operation, first the
word address must be set. This is done by sending
the word address to the AM24LC21 as part of a
write operation. After the word address is sent, the
master generates a start condition following the
acknowledge. This terminates the write operation,
but not before the internal address pointer is set.
Then the master issues the control byte again but
with the R/W bit set to a ‘1’. The AM24LC21 will
then issue an acknowledge and transmits the eight
bit data word.The master will not acknowledge the
transfer but does generate a stop condition and the
AM24LC21 discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a
ran-dom read except that after the AM24LC21
transmits the first data byte, the master issues an
acknowledge as opposed to a stop condition in a
random read. This directs the AM24LC21 to
transmit the next sequentially addressed 8-bit word
(see Figure 7-3).
To provide sequential reads the AM24LC21
contains an internal address pointer which is
incremented by one at the completion of each
operation. This address pointer allows the entire
memory contents to be serially read during one
operation.
7.4 Noise protection
The AM24LC21 employs a VCC threshold detector
circuit which disables the internal erase/write logic if
the VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
P
S
T
O
P
N
O
A
C
K
A
C
K
S
S
T
A
R
T
Control
Byte
Data(n)
Bus activity
SDA Line
Bus activity
Master
Figure 7-1. Current address read
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| AM24LC21S | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| AM24LC21SA | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
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參數(shù)描述 |
|---|---|
| AM24LC21S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
| AM24LC21SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM |
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